Analog-digital, digital-analog converter for a digital control system simulator
Analog-to-digital and digital-to-analog converters for digital control system simulation
COMPUTER SIMULATION↗
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Development of a computer program to obtain ordinates for NACA 4-digit, 4-digit modified, 5-digit, and 16 series airfoils
A computer program developed to calculate the ordinates and surface slopes of any thickness, symmetrical or cambered NACA airfoil of the 4-digit, 4-digit modified, 5-digit, and 16-series airfoil families is presented. The program produces plots of the airfoil nondimensional ordinates and a punch card output of ordinates in the input format of a readily available program for determining the pressure distributions of arbitrary airfoils in subsonic potential viscous flow.
Ladson, C. L.↗
DESDynI Quad First Stage Processor - A Four Channel Digitizer and Digital Beam Forming Processor
The proposed Deformation, Eco-Systems, and Dynamics of Ice Radar (DESDynI-R) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with very fine synchronization and digital beam forming are necessary in order to facilitate this new technique. The Quad First Stage Processor (qFSP) was developed to achieve both the processing performance as well as the digitizing fidelity in order to accomplish this sweeping SAR technique. The qFSP utilizes high precision and high-speed analog to digital converters (ADCs), each with a finely adjustable clock distribution network to digitize the channels at the fidelity necessary to allow for digital beam forming. The Xilinx produced FX130T Virtex 5 part handles the processing to digitally calibrate each channel as well as filter and beam form the receive signals. Demonstrating the digital processing required for digital beam forming and digital calibration is instrumental to the viability of the proposed DESDynI instrument. The qFSP development brings this implementation to Technology Readiness Level (TRL) 6. This paper will detail the design and development of the prototype qFSP as well as the preliminary results from hardware tests.
Chuang, Chung-Lun↗
NISAR L-SAR Digital Electronics Subsystem - A Multichannel Distributed Processing System with Synchronous Timing Control for Digital Beam Forming and Multiple Echo Tracking
The NASA-ISRO Synthetic Aperture Radar (NISAR) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with fine synchronization and digital beam forming are necessary in order to facilitate this new technique called SweepSAR. An architecture employing multiple FPGA based digital signal processors has been conceived to facilitate digital calibration on an individual channel basis as well as digital signal processing to optimize the receive signal. On-board processing and data compression has been implemented to reduce the volume of data in order to satisfy the operational requirements of near global coverage for the desired science targets. A novel command and timing architecture was developed to manage this complex system while providing detailed control of individual channel receive window timing required for digital beam forming. The NISAR L-band Digital Electronics Subsystem is the combination of the hardware, firmware and software components architected and implemented to operate this radar and return the desired quantity and quality of data for the science community.
Chuang, Chung-Lun↗
Root-Raised Cosine Filter Implementation That Uses Canonical Signed Digits for High-Speed Digital Filter Applications
NASA Lewis Research Center's Space Communications Division has been investigating high-speed digital filters that can operate at a higher speed than those in current use for a digital modulator and demodulator (modem). Using the Canonical Signed Digits (CSD) number representation for filter coefficients is a very effective way to increase the filter's speed while reducing complexity in the digital filter hardware design. This approach is a good alternative to using an expensive parallel-processing design technique or custom, application-specific integrated circuits. Such integrated circuits may not be suitable for applications that require filter speeds faster than what application-specific integrated circuits digital signal processors can offer for a dedicated channel. When a communication channel is a dedicated, multiplication process--a costly, time-consuming process--it can be greatly simplified by a replacement of the filter coefficients with CSD numbers. A computer code written with the MATLAB software package runs the program and generates CSD-represented filter coefficients that are based on minimizing minimum mean square errors. Also, the Alta Group of Cadence's Signal Processing Workstation is used to simulate and analyze the CSD filter responses. The impulse response of the root-raised cosine filter that is used as a base model is defined. From this filter, a set of coefficients is sampled and stored in a file. For the all coefficients, the optimal CSD number for each coefficient is searched on the basis of the minimum-mean-square-errors criterion. Because the distribution of CSD numbers is not uniform, quantization errors tend to be bigger for coefficients greater than 1/2. To offset errors that occur in a region of coefficients between 1/2 to 1 and to better represent fractions with CSD numbers, an extra nonzero digit is allowed for any coefficients exceeding 1/2. This will greatly improve frequency response as well as intersymbol interference at the receiver. The frequency response of a set of collected CSD-represented filter coefficients was compared with the same filter that was conventionally implemented. Analyses show CSD-implemented filters perform as well as conventional filters. Comparison of eye diagrams and bit-error-rate curves between CSD filters and traditionally implemented filters are almost indistinguishable. However, filter complexity was reduced from almost 3.5 to 1 for CSD filters. Complete computer simulation results are available. In the near future, work will focus on building actual working digital filter hardware in a field programmable gate array (FPGA).
Kim, Heechul↗
Digital Calibration of TR Modules for Real-time Digital Beamforming SweepSAR Architectures
Real-time digital beamforming, combined with lightweight, large aperture reflectors, enable SweepSAR architectures such as that of the proposed DESDynI [Deformation, Ecosystem Structure, and Dynamics of Ice] SAR [Synthetic Aperture Radar] Instrument (or DSI). These new instrument concepts require new methods for calibrating the multiple channels, which must be combined on-board, in real-time. The calibration of current state-of-the-art Electronically Steered Arrays typically involves pre-flight TR (Transmit/Receive) module characterization over temperature, and in-flight correction based on temperature, which ignores the effects of element aging and drifts unrelated to temperature. We are developing new methods for digitally calibrating digital beamforming arrays to reduce development time, risk and cost of precision calibrated TR modules for array architectures by accurately tracking modules' characteristics through closed-loop Digital Calibration, thus tracking systematic changes regardless of temperature. The benefit of this effort is that it would enable a new class of lightweight radar architecture, Digital Beamforming with SweepSAR, providing significantly larger swath coverage than conventional SAR architectures for solid earth and biomass remote sensing, while reducing mission mass and cost. This new instrument concept requires new methods for calibrating the multiple channels, which must be combined on-board, in real-time.
Real-time digital beamforming↗
Analysis of digital matched filtering schemes for digital receiver applications using simulation methods
The next generation of digital receivers for NASA's Deep Space Network is composed of in-phase and quadrature-phase channels. The authors have modeled and simulated a quadrature-phase baseband channel that includes a low-pass filter and a digital matched filter. The simulation is used to study the performance of the three schemes of digital matched filtering that use digital weighted integrate-and-dump filters. Using three methods for calculating the near-optimum matched filter weight coefficients, the simulation results are analyzed for the NRZ and Manchester data formats. The performances of the digital matched filters are studied in the presence of a timing error between the demodulated symbols and the integrate-and-dump filters.
Gevargiz, J. M.↗
Digital Calibration of TR Modules for Real-Tme Digital Beamforming SweepSAR Architectures
Real-time digital beamforming, combined with lightweight, large aperture reflectors, enable a new architecture, which is the baseline for the proposed DESDynI [Deformation, Ecosystem Structure, and Dynamics of Ice] SAR [Synthetic Aperture Radar] Instrument (or DSI). This new instrument concept requires new methods for calibrating multiple simultaneous channels. The calibration of current state-of-the-art Electronically Steered Arrays typically involves pre-flight TR (Transmit/Receive) module characterization over temperature, and in-flight correction based on measured temperatures. This method ignores the effects of element aging and any drifts unrelated to temperature. We are developing new digital calibration of digital beamforming arrays, which helps to reduce development time, risk and cost. Precision calibrated TR modules enable real-time beamforming architectures by accurately tracking modules' characteristics through closed-loop digital calibration, which tracks systematic changes regardless of temperature. The benefit of this effort is that it would enable a new, lightweight radar architecture, with on-board digital beamforming. This provides significantly larger swath coverage than conventional SAR architectures
Hoffman, James Patrick↗
Digital Engineering at Goddard: Exploring the Digital Thread
Systems are changing and engineering practices must mind the balance between evolutionary and revolutionary change as we move towards increasingly agile processes, enabled by interconnected tools, to best provide for partnered collaboration. The Digital Thread is a foundational capability for a functional Digital Engineering Ecosystem, which is Phase 1 of Goddard's Digital Engineering strategy in an effort to achieve Goddard 2040 vision.
Digital Engineering↗
Digital canopus tracker digital electronics
Circuitry has been developed for digital control of the Canopus tracker. A feasibility and demonstration breadboard has been constructed using microelectronic integrated circuits. The breadboard contains the digital circuits necessary for closed-digital logic necessary for star acquisition, particle rejection, programmable gate selection, cone angle selection, and routing of the digital roll error signal.
Crawford, W. E.↗
Signal-to-noise ratio estimation in digital computer simulation of lowpass and bandpass systems with applications to analog and digital communications, volume 3
Techniques are developed to estimate power gain, delay, signal-to-noise ratio, and mean square error in digital computer simulations of lowpass and bandpass systems. The techniques are applied to analog and digital communications. The signal-to-noise ratio estimates are shown to be maximum likelihood estimates in additive white Gaussian noise. The methods are seen to be especially useful for digital communication systems where the mapping from the signal-to-noise ratio to the error probability can be obtained. Simulation results show the techniques developed to be accurate and quite versatile in evaluating the performance of many systems through digital computer simulation.
Tranter, W. H.↗
Highly integrated digital electronic control: Digital flight control, aircraft model identification, and adaptive engine control
The highly integrated digital electronic control (HIDEC) program at NASA Ames Research Center, Dryden Flight Research Facility is a multiphase flight research program to quantify the benefits of promising integrated control systems. McDonnell Aircraft Company is the prime contractor, with United Technologies Pratt and Whitney Aircraft, and Lear Siegler Incorporated as major subcontractors. The NASA F-15A testbed aircraft was modified by the HIDEC program by installing a digital electronic flight control system (DEFCS) and replacing the standard F100 (Arab 3) engines with F100 engine model derivative (EMD) engines equipped with digital electronic engine controls (DEEC), and integrating the DEEC's and DEFCS. The modified aircraft provides the capability for testing many integrated control modes involving the flight controls, engine controls, and inlet controls. This paper focuses on the first two phases of the HIDEC program, which are the digital flight control system/aircraft model identification (DEFCS/AMI) phase and the adaptive engine control system (ADECS) phase.
Baer-Riedhart, Jennifer L.↗
NASA Earth Science Technology Office (ESTO) Advanced Information Systems Technology (AIST) Program: Earth Systems Digital Twins (ESDT) Standards for Interoperable Digital Twins Workshop Presentations
On September 18, 2023, NASA Earth Science Technology Office (ESTO) Advanced Information Systems Technology (AIST) Program conducted a mini-workshop that brought together seven experts to survey and discuss "Standards for Interoperable Digital Twins". Since three years, the AIST Program has been developing technologies and prototypes for Earth System Digital Twins (ESDT). During those developments and after the ESDT Workshop held in October 2022, it became clear that standard for ESDT interoperability were needed and should be defined as soon as possible. To address this challenge, the AIST program will survey ongoing development for Digital Twins standards in various domains and the September 18, 2023 Workshop represented the first step towards this understanding. Speakers during this event included: Michael Grieves (Digital Twin Institute), Siri Jodha Singh Khalsa (IEEE GRSS Standards), Trent Tinker (OGC), Ryan Berkheimer (NOAA), John Stone (NVIDIA), Thomas Geenen (ECMWF-DestinE) and Arne Berre (SINTEF-Iliad DTO and EDITO). This presentation regroups all the speakers' presentations.
Earth Science Remote Sensing; Information Systems↗
Advanced transducers. Phase A - Investigation of digital transducers and digital compatibility techniques
Digital transducers and digital compatibility - analog-to-digital conversion techniques
ANALOG-TO-DIGITAL CONVERTER↗
A gallium-arsenide digital phase shifter for clock and control signal distribution in high-speed digital systems
The design, implementation, testing, and applications of a gallium-arsenide digital phase shifter and fan-out buffer are described. The integrated circuit provides a method for adjusting the phase of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described chip can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fan-out buffer and provides 12 in-phase outputs. The chip is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components.
Fouts, Douglas J.↗
Parallel digital modem using multirate digital filter banks
A new class of architectures for an all-digital modem is presented in this report. This architecture, referred to as the parallel receiver (PRX), is based on employing multirate digital filter banks (DFB's) to demodulate, track, and detect the received symbol stream. The resulting architecture is derived, and specifications are outlined for designing the DFB for the PRX. The key feature of this approach is a lower processing rate then either the Nyquist rate or the symbol rate, without any degradation in the symbol error rate. Due to the freedom in choosing the processing rate, the designer is able to arbitrarily select and use digital components, independent of the speed of the integrated circuit technology. PRX architecture is particularly suited for high data rate applications, and due to the modular structure of the parallel signal path, expansion to even higher data rates is accommodated with each. Applications of the PRX would include gigabit satellite channels, multiple spacecraft, optical links, interactive cable-TV, telemedicine, code division multiple access (CDMA) communications, and others.
Sadr, Ramin↗
Canonical Signed Digit Study: FIR Digital Filter Simulation Results - Part 2
Finite Impulse Response digital filter using Canonical Signed-Digit (CSD) number representation for the coefficients has been studied and its computer simulation results are presented here. Minimum Mean Square Error (MMSE) criterion is employed to optimize filter coefficients into the corresponding CSD numbers. To further improve coefficients optimization process, an extra non-zero bit is added for any filter coefficients exceeding 1/2. This technique improves frequency response of filter without increasing filter complexity almost at all. The simulation results show outstanding performance in bit-error-rate (BER) curve for all CSD implemented digital filters included in this presentation material.
Kim, Heechul↗
Comparison of MPEG-1 digital videotape with digitized sVHS videotape for quantitative echocardiographic measurements
Digital format is rapidly emerging as a preferred method for displaying and retrieving echocardiographic studies. The qualitative diagnostic accuracy of Moving Pictures Experts Group (MPEG-1) compressed digital echocardiographic studies has been previously reported. The goals of the present study were to compare quantitative measurements derived from MPEG-1 recordings with the super-VHS (sVHS) videotape clinical standard. Six reviewers performed blinded measurements from still-frame images selected from 20 echocardiographic studies that were simultaneously acquired in sVHS and MPEG-1 formats. Measurements were obtainable in 1401 (95%) of 1486 MPEG-1 variables compared with 1356 (91%) of 1486 sVHS variables (P <.001). Excellent agreement existed between MPEG-1 and sVHS 2-dimensional linear measurements (r = 0.97; MPEG-1 = 0.95[sVHS] + 1.1 mm; P <.001; Delta = 9% +/- 10%), 2-dimensional area measurements (r = 0.89), color jet areas (r = 0.87, p <.001), and Doppler velocities (r = 0.92, p <.001). Interobserver variability was similar for both sVHS and MPEG-1 readings. Our results indicate that quantitative off-line measurements from MPEG-1 digitized echocardiographic studies are feasible and comparable to those obtained from sVHS.
NASA Discipline Cardiopulmonary↗