Results for “early fault-tolerant processors”

Modeling methods for the design and evaluation of fault-tolerant systems

The authors describe an approach for using directed graph simulation models, behavioral simulation models, and semi-Markov analytic models to implement early- to mid-design analysis activities specified by the SDIO BM/C3 Processor and Algorithm Working Group. The use of the models was demonstrated for a mission scenario requiring parallel, reliable computations with a maximum probability of system failure between 10-4 and 10-2 over a 5-year-preengagement phase and between 10-7 and 10-5 over a half-hour engagement phase.