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DOE OSTI2022

Advanced Power Electronics Designs - Reliability and Prognostics (Keystone Project 1)

The primary deliverable for this project will be to construct a power electronics package utilizing an organic electrically insulating substrate material with a direct chip-to-chip interconnect technology and demonstrate superior thermal performance and greater reliability under thermal cycling, thermal aging, vibration, power cycling, and electrical high-potential evaluation over traditional packages.

ADVANCED PROPULSION SYSTEMS↗

DOE OSTI2023

Advanced Power Electronics Designs - Reliability and Prognostics (Keystone Project 1)

ADVANCED PROPULSION SYSTEMS,ENGINEERING↗

DOE OSTI2025

Thermal Management for Planar Package Power Electronics (CRADA Final Report)

The National Renewable Energy Laboratory (NREL) and John Deere Electronic Solutions (JDES) collaborated to develop and evaluate computer models and simulations related to the thermal performance of semiconductor device packaging for an inverter of an off-road vehicle ("Semiconductor Packaging"). The objective of the research was for NREL and JDES to develop a two or three-dimensional computer-aided design model of the Semiconductor Packaging ("Computer Model") for thermal performance evaluation in a simulation. The project developed computer models of a Semiconductor Package of silicon-carbide semiconductor devices with appropriate thermal dissipation via one or more of the following thermal features: a double-sided planar cooling configuration, an air-cooled configuration, a liquid-cooled configuration for off-road inverter applications in a relevant simulated operating environment. It is noted that surface area and prototype product embodiment consisting of air-cooled and liquid-cooled configurations may and may not be in direct contact with power semiconductor chips. The idea was to explore and develop packaging and thermal management technology for power semiconductors that was most effective in the performance yet had least burden in overall product cost for a given application.

33 ADVANCED PROPULSION SYSTEMS↗

DOE OSTI2021

A 24-Channel Digitizer With a JESD204B-Compliant Serial Interface for High-Speed Detectors

In this report a 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm 2 , is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) < 0.55 LSB, input-referred thermal noise of $114.5 μV-rms, and a bit error rate (BER) of better than 10-14. The power dissipation is 98 mW/channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2020

W-band system-on-chip electron cyclotron emission imaging system on DIII-D

Monolithic, millimeter wave “system-on-chip” (SoC) technology has been employed in heterodyne receiver integrated circuit radiometers in a newly developed Electron Cyclotron Emission Imaging (ECEI) system on the DIII-D tokamak for 2D electron temperature profile and fluctuation evolution diagnostics. Here, a prototype module operating in E-band (72-80 GHz) was first employed in a 2 x 10 element array that demonstrated significant improvements over the previous quasi-optical Schottky diode mixer arrays during the 2018 operational campaign of the DIII-D tokamak. For compatibility with International Thermonuclear Experimental Reactor (ITER) relevant scenarios on DIII-D, the SoC ECEI system was upgraded with 20 horn-waveguide receiver modules. Each individual module contains a University of California at Davis designed W-band (75 -110 GHz) receiver die that integrates a broadband low noise amplifier (LNA), a double balanced down-converting mixer, and a x4 multiplier on the local oscillator (LO) chain. A x2 multiplier and two IF amplifiers are packaged and selected to further boost the signal strength as well as downconvert the signal frequency. The upgraded W-band array exhibits > 30 dB additional gain and 20x improvement in noise temperature comparing with the previous Schottky diode radio frequency (RF) mixer input systems; an internal 8 times multiplier chain is used to bring down the LO frequency below 12 GHz, thereby obviating the need for a large aperture for quasi-optical LO coupling and replacing it with coaxial connectors. The horn-waveguide shielding housing avoids out-of-band noise interference on each individual module. The upgraded ECEI system plays an important role for absolute electron temperature evolution and fluctuation measurements for edge and core region transport physics studies.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

DOE OSTI2024

Giant energy storage and power density negative capacitance superlattices

Dielectric electrostatic capacitors, because of their ultrafast charge-discharge, are desirable for high-power energy storage applications. Along with ultrafast operation, on-chip integration can enable miniaturized energy storage devices for emerging autonomous microelectronics and microsystems. Moreover, state-of-the-art miniaturized electrochemical energy storage systems-microsupercapacitors and microbatteries-currently face safety, packaging, materials and microfabrication challenges preventing on-chip technological readiness, leaving an opportunity for electrostatic microcapacitors. Here, in this study, we report record-high electrostatic energy storage density (ESD) and power density, to our knowledge, in HfO 2 -ZrO 2 -based thin film microcapacitors integrated into silicon, through a three-pronged approach. First, to increase intrinsic energy storage, atomic-layer-deposited antiferroelectric HfO 2 -ZrO 2 films are engineered near a field-driven ferroelectric phase transition to exhibit amplified charge storage by the negative capacitance effect, which enhances volumetric ESD beyond the best-known back-end-of-the-line-compatible dielectrics (115 J cm -3 ). Second, to increase total energy storage, antiferroelectric superlattice engineering scales the energy storage performance beyond the conventional thickness limitations of HfO 2 -ZrO 2 -based (anti)ferroelectricity (100-nm regime). Third, to increase the storage per footprint, the superlattices are conformally integrated into three-dimensional capacitors, which boosts the areal ESD nine times and the areal power density 170 times that of the best-known electrostatic capacitors: 80 mJ cm -2 and 300 kW cm -2 , respectively. This simultaneous demonstration of ultrahigh energy density and power density overcomes the traditional capacity-speed trade-off across the electrostatic-electrochemical energy storage hierarchy. Furthermore, the integration of ultrahigh-density and ultrafast-charging thin films within a back-end-of-the-line-compatible process enables monolithic integration of on-chip microcapacitors, which can unlock substantial energy storage and power delivery performance for electronic microsystems.

25 ENERGY STORAGE↗