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Additional developmental work on the existing programmable electronic controller and hydronic package for use with solar heating and cooling systems is summarized. The controller/hydronics subsystems passed all acceptance tests and performance criteria. The subsystems were shown marketable for public use.
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The analysis, design, and development work to reduce the weight and size of a standard modular power supply with a 350 watt output was summarized. By integrating low cost commercial heat pipes in the redesign of this power supply, weight was reduced by 30% from that of the previous design. The temperature was also appreciably reduced, increasing the environmental capability of the unit. A demonstration unit with a 100 watt output and a 15 volt regulator module, plus simulated output modules, was built and tested to evaluate the thermal performance of the redesigned power supply.
This report provides evaluation methodology guidance based on previous National Aeronautics and Space Administration (NASA) reports and literature surveys for 3D stack packages and assemblies. Two aspects of technology are covered: the package itself (guidance for functional packages) and package assembly manufacturing and reliability. This work was funded by the NASA Electronic Parts and Packaging (NEPP) Program. The objectives of this NEPP project are to: Perform a literature survey of 3D stack technology; perform a literature survey on the evaluation methodology for 3D package and assembly; combine the two aspects to provide evaluation methodology for both aspects with consideration of interactions between package and assembly; generate guidance on the evaluation methodology for 3D stack package integrity prior to and after assembly; provide recommendations on future experimental activities. The qualification and evaluation methodology guidelines will facilitate NASA projects in effectively evaluating the reliability of very dense and newly available high-density 3D stack packages, allowing more processing power in a smaller board footprint and lower system weight.
Microprocessor, Graphics Processing Units (GPUs) and DDRx memory devices have emerged as promising next-generation technologies that enables both high performance processing and acceleration of complex algorithms for the latest challenges in human spaceflight, autonomous vehicles and artificial intelligence (AI). The feature sets of these devices offer exponential increases to throughput, calculation capability and system autonomy when compared to legacy flight systems. NASA's Electronic Part and Packaging (NEPP) Program has conducted an investigation into the radiation susceptibility of leading edge devices and process technologies by establishing standardized test approaches. Unlike most discrete devices, these require state of the art test systems to induce specific hardware activity similar to application software, thus allowing the characterization of failure modes within the system. To best characterize the tested part, NEPP eliminates variables that may impact device performance under radiation. Simplification of remaining system-level variables leads to an improved understanding of complex computational devices and their intended applications. The failure modes and error signatures that are recorded during testing are used to determine radiation sensitivity of the semiconductor process and the microcode architecture of the design. This presentation will discuss the test methodology that NASA Electronic Parts and Packaging (NEPP) is working to establish for its microprocessor, GPU and DDRx memory test programs to provide guidance on these devices and their underlying technology, in regards to their potential usage in future space flight systems.
This book of knowledge (BoK) provides a critical review of the benefits and difficulties associated with using proton irradiation as a means of exploring the radiation hardness of commercial-off-the-shelf (COTS) systems. This work was developed for the NASA Electronic Parts and Packaging (NEPP) Board Level Testing for the COTS task. The fundamental findings of this BoK are the following. The board-level test method can reduce the worst case estimate for a board's single-event effect (SEE) sensitivity compared to the case of no test data, but only by a factor of ten. The estimated worst case rate of failure for untested boards is about 0.1 SEE/board-day. By employing the use of protons with energies near or above 200 MeV, this rate can be safely reduced to 0.01 SEE/board-day, with only those SEEs with deep charge collection mechanisms rising this high. For general SEEs, such as static random-access memory (SRAM) upsets, single-event transients (SETs), single-event gate ruptures (SEGRs), and similar cases where the relevant charge collection depth is less than 10 μm, the worst case rate for SEE is below 0.001 SEE/board-day. Note that these bounds assume that no SEEs are observed during testing. When SEEs are observed during testing, the board-level test method can establish a reliable event rate in some orbits, though all established rates will be at or above 0.001 SEE/board-day. The board-level test approach we explore has picked up support as a radiation hardness assurance technique over the last twenty years. The approach originally was used to provide a very limited verification of the suitability of low cost assemblies to be used in the very benign environment of the International Space Station (ISS), in limited reliability applications. Recently the method has been gaining popularity as a way to establish a minimum level of SEE performance of systems that require somewhat higher reliability performance than previous applications. This sort of application of the method suggests a critical analysis of the method is in order. This is also of current consideration because the primary facility used for this type of work, the Indiana University Cyclotron Facility (IUCF) (also known as the Integrated Science and Technology (ISAT) hall), has closed permanently, and the future selection of alternate test facilities is critically important. This document reviews the main theoretical work on proton testing of assemblies over the last twenty years. It augments this with review of reported data generated from the method and other data that applies to the limitations of the proton board-level test approach. When protons are incident on a system for test they can produce spallation reactions. From these reactions, secondary particles with linear energy transfers (LETs) significantly higher than the incident protons can be produced. These secondary particles, together with the protons, can simulate a subset of the space environment for particles capable of inducing single event effects (SEEs). The proton board-level test approach has been used to bound SEE rates, establishing a maximum possible SEE rate that a test article may exhibit in space. This bound is not particularly useful in many cases because the bound is quite loose. We discuss the established limit that the proton board-level test approach leaves us with. The remaining possible SEE rates may be as high as one per ten years for most devices. The situation is actually more problematic for many SEE types with deep charge collection. In cases with these SEEs, the limits set by the proton board-level test can be on the order of one per 100 days. Because of the limited nature of the bounds established by proton testing alone, it is possible that tested devices will have actual SEE sensitivity that is very low (e.g., fewer than one event in 1 × 10(exp 4) years), but the test method will only be able to establish the limits indicated above. This BoK further examines other benefits of proton board-level testing besides hardness assurance. The primary alternate use is the injection of errors. Error injection, or fault injection, is something that is often done in a simulation environment. But the proton beam has the benefit of injecting the majority of actual SEEs without risk of something being missed, and without the risk of simulation artifacts misleading the SEE investigation.
With the rapidly increasing insertion of photonic devices, circuits and subsystems into NASA spacecraft, a variety of issues associated with reliability and radiation tolerance have arisen. In this paper, we discuss these issues from the perspective of the work currently ongoing in the NASA Electronic Parts and Packaging (NEPP) Program. This Program is focused on evaluating the reliability and radiation response of advanced and emerging microelectronics and photonics technologies of interest to NASA spacecraft system designers.
A simulator is being built to determine the practicality of using an advanced avionics system in a helicopter. Features include an autopilot; a navigation and flight planning component; an advisory system built into the computer; conventional gages and displays; a clock function; a fuel totalizer; a weight and balance computator; a performance evaluator; and emergency and normal checklists. The translation of a computer program written in PASCAL into a form that can be read by the graphics package for the simulator and basic electronic work in simulator construction are discussed.
Electronic systems in aerospace and in space exploration missions are expected to encounter extreme temperatures and wide thermal swings. To address the needs for extreme temperature electronics, research efforts exist at the NASA Glenn Research Center (GRC) to develop and evaluate electronics for extreme temperature operations, and to establish their reliability under extreme temperature operation and thermal cycling; conditions that are typical of both the aerospace and space environments. These efforts are supported by the NASA Fundamental Aeronautics/Subsonic Fixed Wing Program and by the NASA Electronic Parts and Packaging (NEPP) Program. This work reports on the results obtained on the development of a temperature sensor geared for use in harsh environments.
Recent work for the NASA Electronic Parts and Packaging Program Power MOSFET task is presented. The Task technology focus, roadmap, and partners are given. Recent single-event effect test results on commercial, automotive, and radiation hardened trench power MOSFETs are summarized with an emphasis on risk of using commercial and automotive trench-gate power MOSFETs in space applications.
A brief overview is presented of the sensors and electronics development work ongoing at NASA Glenn Research Center which is intended to meet the needs of future aerospace applications. Three major technology areas are discussed: 1) high temperature SiC electronics, 2) SiC gas sensor technology development, and 3) packaging of harsh environment devices. Highlights of this work include world-record operation of SiC electronic devices including 500?C JFET transistor operation with excellent properties, atomically flat SiC gas sensors integrated with an on-chip temperature detector/heater, and operation of a packaged AC amplifier. A description of the state-of-the-art is given for each topic. It is concluded that significant progress has been made and that given recent advancements the development of high temperature smart sensors is envisioned.
Microelectromechanical systems (MEMS) have shown a significant promise in the last decade for a variety of applications such as air-bag, pressure sensors, accelerometer, microgyro, etc. Standard semiconductor microelectronics packaging needs the integrated circuits to be protected from the harsh environment, and provide electrical communication with the other parts of the circuit, facilitate thermal dissipation efficiently, and impart mechanical strength to the silicon die. Microelectronics packaging involves wafer dicing, bonding, lead attachment, encapsulation to protect from the environment, electrical integrity, and package leak tests to assure the packaging technology. In the case of MEMS the microstructures (active elements) often interfaces with the hostile environment where packaging leak tests and testing of such devices using chemical and mechanical parameters will be very difficult and expensive. Packaging of MEMS is significantly complex as they serve to protect from the environment and microstructures interact with the same environment to measure or affect the desired physical or chemical parameters. The most of the silicon circuitry is sensitive to temperature, moisture, magnetic field, light, and electromagnetic interference. The package must then protect the on-board silicon circuitry while simultaneously exposing the microsensor to the effect it 'measures to assure the MEMS technology by lowering the risk to zero. MEMS technology has a major application in developing a microspacecraft for space systems provided assurance of MEMS technology is sufficiently addressed nondestructively. This technology would eventually miniaturize many of the components of the spacecraft to reach the NASA's safety and mission assurance goal by building faster, cheaper, better, smaller spacecraft to explore the space more effectively by teaming-up with the other NASA centers using the limited resources available. This paper discusses the latest developments in the MEMS technology and challenging issues in the packaging of hermetically sealed and non-hermetically sealed MEMS sensor devices based on silicon, poly-silicon, and other materials for microspacecraft applications considering the space environment and reliability assurance qualification guidelines in perspective. Acknowledgments: The above research work is supported by the NASA Electronics Parts and Packaging Program (NEPP) and performed by the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA under a contract with the NASA - Code Q for the Office of Safety and Mission Assurance Program 323-79.
This work is sponsored by the NASA Electronic Parts and Packaging (NEPP) Program. One of the objectives of this task is to prepare a body of knowledge guideline document summarizing the CMOS technology scaling impact on CMOS parts and parts reliability for space applications. Scaling impact on parts radiation sensitivity is not addressed in this report.
The purpose of this presentation is to familiarize the people attending the JEDEC work meetings about the NEPP Program, and recent tasks we have undertaken. There is a description of the policy and testing guidelines in development and an explanation of the Government Working Group, a collaboration of several US government space agencies that come together to discuss topics relating to the reliable use of electronics. The presentation also includes a brief description of recent NASA accomplishments such as the launching/splash down of the SpaceX Crew Dragon and the launch of the next Mars rover.
The purpose of this presentation is to familiarize the people attending the JEDEC work meetings about the NEPP Program, and recent tasks we have undertaken. There is a description of the policy and testing guidelines in development and an explanation of the Government Working Group, a collaboration of several US government space agencies that come together to discuss topics relating to the reliable use of electronics. The presentation also includes a brief description of NASA events such as the landing of the next Mars rover in Feb 2021.
A hollow cathode plasma contactor has been baselined as a charge control device for the Space Station (SS) to prevent deleterious interactions of coated structural components with the ambient plasma. NASA LeRC Work Package 4 initiated the development of a plasma contactor system comprised of a Power Electronics Unit (PEU), an Expellant Management Unit (EMU), a command and data interface, and a Plasma Contactor Unit (PCU). A breadboard PEU was designed and fabricated. The breadboard PEU contains a cathode heater and discharge power supply, which were required to operate the PCU, a control and auxiliary power converter, an EMU interface, a command and telemetry interface, and a controller. The cathode heater and discharge supplies utilized a push-pull topology with a switching frequency of 20 kHz and pulse-width-modulated (PWM) control. A pulse ignition circuit derived from that used in arcjet power processors was incorporated in the discharge supply for discharge ignition. An 8088 based microcontroller was utilized in the breadboard model to provide a flexible platform for controller development with a simple command/data interface incorporating a direct connection to SS Mulitplexer/Demultiplexer (MDM) analog and digital I/O cards. Incorporating this in the flight model would eliminate the hardware and software overhead associated with a 1553 serial interface. The PEU autonomously operated the plasma contactor based on command inputs and was successfully integrated with a prototype plasma contactor unit demonstrating reliable ignition of the discharge and steady-state operation.
The eighth day of the STS-82 mission begins with the crew, Commander Kenneth D. Bowersox, Pilot Scott J. Horowitz, Payload Commander Mark C. Lee, and Mission Specialists Gregory J. Harbaugh, Steven L. Smith, Joseph R. Tanner, and Steven A. Hawley performing the final spacewalk of the mission. Lee and Smith attach several thermal insulation blankets to three equipment compartments at the top of the Support Systems Module section of Hubble which contain key data processing, electronics and scientific instrument telemetry packages. Following the completion of that work, Lee and Smith briefly return to the airlock while flight controllers evaluated a possible glitch with one of four Reaction Wheel Assembly units in Hubble used to maneuver the telescope for its scientific observations. A spare Reaction Wheel Assembly was available aboard Discovery for a swap out during an additional spacewalk had it been necessary, but a few hours later, after further analysis, payload controllers reported that the Reaction Wheel Assembly was in excellent shape and operating at the proper speed.
Due to low ESR and safe failure mode, new technology chip polymer tantalum capacitors (CPTC) have gained popularity in the electronics design community, first in commercial applications, and now in hi-rel and space systems. The major drawbacks of these parts are high leakage currents, degradation under environmental stresses, and a relatively narrow temperature range of operating and storage conditions. Several studies have shown that a certain amount of moisture in polymer cathodes is necessary for a normal operation of the parts. This might limit applications of CPTCs in space systems and requires analysis of long-term exposure to deep vacuum conditions on their performance and reliability. High leakage currents and limited maximum operational temperature complicate accelerated testing that is necessary to assess long-term reliability and require new screening and qualification procedures for quality assurance. A better understanding of behavior of CPTCs as compared to traditional, MnO2, capacitors is necessary to develop adequate approaches for QA system for space applications. A specific of CPTCs is that different materials and processes might be used for low-voltage (10 V and less) and high-voltage (above 10 V) capacitors, so performance and degradation processes in these groups require separate analysis. In this work, that is a part of the NASA Electronic Parts and Packaging (NEPP) program, degradation of AC and DC characteristics under environmental stresses at different temperatures and voltages have been studied in nine lots of commercial and automotive grade capacitors rated to 10 V. Results of analysis of leakage currents, high temperature storage (HTS) up to 5000 hrs in vacuum and air at different temperatures, and Highly Accelerated Life Testing (HALT) in the range from 85 C to 145 C are presented. Temperature and voltage acceleration factors were calculated based on approximation of distributions of degradation rates with a general log-linear Weibull model. Mechanisms of degradation and failures, and requirements for screening and qualification testing are discussed.