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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2015

Dielectric properties of inorganic fillers filled epoxy thin film

The demand on the small size and high performance electronics has driven changes in the electronic packaging requirements from discrete capacitor to embedded capacitor. Embedded capacitor can improve electrical performance compared with discrete capacitor. This study aimed to achieve high dielectric of epoxy thin film composite that were targeted for application as embedded capacitor. In this study, inorganic fillers such as Calcium Copper Titanate (CCTO), Iron(III) Oxide (Fe{sub 2}O{sub 3}) and Titanium Dioxide (TiO{sub 2}) were loaded in epoxy system at 5 and 20vol%. Morphology and dielectric properties were investigated to identify the effect of fillers loading and types of fillers on the properties of epoxy thin film composite. Based on the study, CCTO with 20vol% loading was found to have good dielectric properties compared to other type of fillers.

36 MATERIALS SCIENCE↗
DOE OSTI2014

High energy storage capacitor by embedding tunneling nano-structures

In an All-Electron Battery (AEB), inclusions embedded in an active region between two electrodes of a capacitor provide enhanced energy storage. Electrons can tunnel to/from and/or between the inclusions, thereby increasing the charge storage density relative to a conventional capacitor. One or more barrier layers is present in an AEB to block DC current flow through the device. The AEB effect can be enhanced by using multi-layer active regions having inclusion layers with the inclusions separated by spacer layers that don't have the inclusions. The use of cylindrical geometry or wrap around electrodes and/or barrier layers in a planar geometry can enhance the basic AEB effect. Other physical effects that can be employed in connection with the AEB effect are excited state energy storage, and formation of a Bose-Einstein condensate (BEC).

25 ENERGY STORAGE↗
NASA NTRS2006

Embedded Resistors and Capacitors in Organic and Inorganic Substrates

Embedded resistors and capacitors were purchased from two technology; organic PWB and inorganic low temperature co-fire ceramic (LTCC). Small groups of each substrate were exposed to four environmental tests and several characterization tests to evaluate their performance and reliability. Even though all passive components maintained electrical performance throughout environmental testing, differences between the two technologies were observed. Environmental testing was taken beyond manufacturers' reported testing, but general not taken to failure. When possible, data was quantitatively compared to manufacturer's data.

printed circuit board (PCB)↗
DOE OSTI2024

2D material platform for overcoming the amplitude–phase tradeoff in ring resonators

Compact and high-speed electro-optic phase modulators play a vital role in various large-scale applications including optical computing, quantum and neural networks, and optical communication links. Conventional electro-refractive phase modulators such as silicon (Si), III-V and graphene on Si suffer from a fundamental tradeoff between device length and optical loss that limits their scaling capabilities. High-finesse ring resonators have been traditionally used as compact intensity modulators, but their use for phase modulation has been limited due to the high insertion loss associated with the phase shift. Here, we show that high-finesse resonators can achieve a strong phase shift with low insertion loss by simultaneous modulation of the real and imaginary parts of the refractive index, to the same extent, i.e., Δ n Δ k ∼1. To implement this strategy, we demonstrate an active hybrid platform that combines a low-loss SiN ring resonator with 2D materials such as graphene and transition metal dichalcogenide [tungsten disulphide (WSe 2 )], which induces a strong change in the imaginary and real parts of the index. Our platform consisting of a 25 µm long Gr-Al 2 O 3 -WSe 2 capacitor embedded on a SiN ring of 50 µm radius (∼8% ring coverage) achieves a continuous phase shift of (0.46±0.05) π radians with an insertion loss (IL) of 3.18±0.20 dB and a transmission modulation (Δ T Ring ) of 1.72±0.15dB at a probe wavelength ( λ p ) of 1646.18 nm. We find that our Gr-Al 2 O 3 -WSe 2 capacitor exhibits a phase modulation efficiency ( V π 2 ⋅ L ) of 0.530±0.016V⋅cm and can support an electro-optic bandwidth of 14.9±0.1GHz. We further show that our platform can achieve a phase shift of π radians with an IL of 5 dB and a minimum Δ T of 0.046 dB. We demonstrate the broadband nature of the binary phase response, by measuring a phase shift of (1.00±0.10) π radians, with an IL of 5.20±0.31dB and a minimal Δ T Ring of 0.015±0.006dB for resonances spanning from 1564 to 1650 nm. This SiN–2D hybrid platform provides the design for compact and high-speed reconfigurable circuits with graphene and transition metal dichalcogenide (TMD) monolayers that can enable large-scale photonic systems.

Datta, Ipshita (ORCID:0000000318842882)↗
NASA NTRSDate not supplied

Design and Assembly Process Implementation for Embedding Passive and Active Components Introduction to IPC-7092

"This presentation describes the design and assembly challenges for implementing passive and active components, in either formed or inserted methodology, into a printed board. The completed structure including internal electronic components is ready for surface mount and/or through-hole component attachment. The multilayered structure becomes a complete product ready for further processing in an assembly process and be made from organic, inorganic (ceramic) or both types of material."

embedded circuitry↗
NASA NTRS2020

An Embedded Planar-Foil Capacitor Material, FPGA Based Interposer, Aimed at Improving System Performance and Reduced Board Size for Space Based Electronics

This paper presents our work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuit (ASIC) applications. FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. Our interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry. Our Interposer focuses on the needs of Micro Semi’s RTG4 FPGA. We developed the interposer using COTS embedded foil capacitors. The Interposer is customized to the capacitance requirements for each of the FPGA banks. We evaluated three foil manufactures Oak Mitsui, 3M and TDK. The three different designs were evaluated, but we will focus on the Oak-Mitsui based Interposer that we constructed and tested. Through simulations, we validate the horizontal and vertical interconnect inductances, that FPGA decoupling requirements are met. The use of the interposer results in an overall reduction in our Printed Wiring Board (PWB) area.

Hunter, Don J↗
NASA NTRS2020

An embedded planar-foil capacitor material, FPGA based interposer, aimed at improving system performance and reduced board size for space based electronics

This paper presents work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuits (ASIC). FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. The developed interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry.

Cheng, Ben↗
NASA NTRS2003

Development of reliable electronic packaging solutions for spacecraft avionics miniaturization using embedded passice devices

Miniaturization of electronic packages will play a key rule in future space avionics systems. Smaller avionics packages will reduce payloads while providing greater functionality for information processing and mission instrumentation. Current surface mount technology discrete passive devices not only take up significant space but also add weight. To that end, the use of embedded passive devices, such as capacitors, inductors and resistors will be instrumental in allowing electronics to be made smaller and lighter. Embedded passive devices fabricated on silicon or like substrates using thin film technology, promise great savings in circuit volume, as well as potentially improving electrical performance by decreasing parasitic losses. These devices exhibit a low physical profile and allow the circuit footprint to be reduced by stacking passive elements within a substrate. Thin film technologies used to deposit embedded passive devices are improving and costs associated with the process are decreasing.

Schatzel, Don↗
DOE OSTI2014

Mechanical confinement for improved energy storage density in BNT-BT-KNN lead-free ceramic capacitors

With the advent of modern power electronics, embedded circuits and non-conventional energy harvesting, the need for high performance capacitors is bound to become indispensible. The current state-of-art employs ferroelectric ceramics and linear dielectrics for solid state capacitance. However, lead-free ferroelectric ceramics propose to offer significant improvement in the field of electrical energy storage owing to their high discharge efficiency and energy storage density. In this regards, the authors have investigated the effects of compressive stress as a means of improving the energy storage density of lead-free ferroelectric ceramics. The energy storage density of 0.91(Bi{sub 0.5}Na{sub 0.5})TiO{sub 3}-0.07BaTiO{sub 3}-0.02(K{sub 0.5}Na{sub 0.5})NbO{sub 3} ferroelectric bulk ceramic was analyzed as a function of varying levels of compressive stress and operational temperature .It was observed that a peak energy density of 387 mJ.cm{sup -3} was obtained at 100 MPa applied stress (25{sup o}C). While a maximum energy density of 568 mJ.cm{sup -3} was obtained for the same stress at 80{sup o}C. These values are indicative of a significant, 25% and 84%, improvement in the value of stored energy compared to an unloaded material. Additionally, material's discharge efficiency has also been discussed as a function of operational parameters. The observed phenomenon has been explained on the basis of field induced structural transition and competitive domain switching theory.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Memory functions of nanocrystalline cadmium selenide embedded ZrHfO high-k dielectric stack

Metal-oxide-semiconductor capacitors made of the nanocrystalline cadmium selenide nc-CdSe embedded Zr-doped HfO{sub 2} high-k stack on the p-type silicon wafer have been fabricated and studied for their charge trapping, detrapping, and retention characteristics. Both holes and electrons can be trapped to the nanocrystal-embedded dielectric stack depending on the polarity of the applied gate voltage. With the same magnitude of applied gate voltage, the sample can trap more holes than electrons. A small amount of holes are loosely trapped at the nc-CdSe/high-k interface and the remaining holes are strongly trapped to the bulk nanocrystalline CdSe site. Charges trapped to the nanocrystals caused the Coulomb blockade effect in the leakage current vs. voltage curve, which is not observed in the control sample. The addition of the nanocrystals to the dielectric film changed the defect density and the physical thickness, which are reflected on the leakage current and the breakdown voltage. More than half of the originally trapped holes can be retained in the embedded nanocrystals for more than 10 yr. The nanocrystalline CdSe embedded high-k stack is a useful gate dielectric for this nonvolatile memory device.

36 MATERIALS SCIENCE↗
NASA NTRS2009

Embedded passives emulator FY2003 interim report

The National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program has been evaluating state-of-the-art Embedded Passive Technology for the printed circuit board (PCB) industry for the past several years and has conducted its own testing on embedded passive coupons (resistors and capacitors). This document is a progress report of the work performed through fiscal year 2008 by NASA and the Navy to convert an existing PWB (printed wiring board) design to a design that incorporates embedded passive components. The work is being performed through a memorandum of understanding (MOU) between the NEPP Program (NASA) and the Naval Surface Warfare Center (NSWC) Crane Emerging Critical Interconnect Technology (ECIT) Program. NSWC Crane’s ECIT Program has funding to convert two PCB designs from the military and aerospace industry to a PCB design with embedded passives. ECIT will provide a design team that will take a well characterized design and convert it to an embedded design. They will also provide electrical modeling and layout expertise as well as build the PWB in their facility in Indiana. NEPP, through the Jet Propulsion Laboratory (JPL), will assemble any passives deemed not suitable for embedding and the active components and electrically test the new design to the existing (non-embedded) design

Gerke, David↗
DOE OSTI2016

Charge storage and tunneling mechanism of Ni nanocrystals embedded HfO{sub x} film

A nano-floating gate memory structure based on Ni nanocrystals (NCs) embedded HfO{sub x} film is deposited by means of radio-frequency magnetron sputtering. Microstructure investigations reveal that self-organized Ni-NCs with diameters of 4-8 nm are well dispersed in amorphous HfO{sub x} matrix. Pt/Ni-NCs embedded HfO{sub x}/Si/Ag capacitor structures exhibit voltage-dependent capacitance-voltage hysteresis, and a maximum flat-band voltage shift of 1.5 V, corresponding to a charge storage density of 6.0 × 10{sup 12} electrons/cm{sup 2}, is achieved. These capacitor memory cells exhibit good endurance characteristic up to 4 × 10{sup 4} cycles and excellent retention performance of 10{sup 5} s, fulfilling the requirements of next generation non-volatile memory devices. Schottky tunneling is proven to be responsible for electrons tunneling in these capacitors.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS2011

Distributed Capacitive Sensor for Sample Mass Measurement

Previous robotic sample return missions lacked in situ sample verification/ quantity measurement instruments. Therefore, the outcome of the mission remained unclear until spacecraft return. In situ sample verification systems such as this Distributed Capacitive (DisC) sensor would enable an unmanned spacecraft system to re-attempt the sample acquisition procedures until the capture of desired sample quantity is positively confirmed, thereby maximizing the prospect for scientific reward. The DisC device contains a 10-cm-diameter pressure-sensitive elastic membrane placed at the bottom of a sample canister. The membrane deforms under the weight of accumulating planetary sample. The membrane is positioned in close proximity to an opposing rigid substrate with a narrow gap. The deformation of the membrane makes the gap narrower, resulting in increased capacitance between the two parallel plates (elastic membrane and rigid substrate). C-V conversion circuits on a nearby PCB (printed circuit board) provide capacitance readout via LVDS (low-voltage differential signaling) interface. The capacitance method was chosen over other potential approaches such as the piezoelectric method because of its inherent temperature stability advantage. A reference capacitor and temperature sensor are embedded in the system to compensate for temperature effects. The pressure-sensitive membranes are aluminum 6061, stainless steel (SUS) 403, and metal-coated polyimide plates. The thicknesses of these membranes range from 250 to 500 m. The rigid substrate is made with a 1- to 2-mm-thick wafer of one of the following materials depending on the application requirements glass, silicon, polyimide, PCB substrate. The glass substrate is fabricated by a microelectromechanical systems (MEMS) fabrication approach. Several concentric electrode patterns are printed on the substrate. The initial gap between the two plates, 100 m, is defined by a silicon spacer ring that is anodically bonded to the glass substrate. The fabricated proof-of-concept devices have successfully demonstrated tens to hundreds of picofarads of capacitance change when a simulated sample (100 g to 500 g) is placed on the membrane.

Toda, Risaku↗
DOE OSTI2014

Polarization of Bi{sub 2}Te{sub 3} thin film in a floating-gate capacitor structure

Metal-Oxide-Semiconductor (MOS) capacitors with Bi{sub 2}Te{sub 3} thin film sandwiched and embedded inside the oxide layer have been fabricated and studied. The capacitors exhibit ferroelectric-like hysteresis which is a result of the robust, reversible polarization of the Bi{sub 2}Te{sub 3} thin film while the gate voltage sweeps. The temperature-dependent capacitance measurement indicates that the activation energy is about 0.33 eV for separating the electron and hole pairs in the bulk of Bi{sub 2}Te{sub 3}, and driving them to either the top or bottom surface of the thin film. Because of the fast polarization speed, potentially excellent endurance, and the complementary metal–oxide–semiconductor compatibility, the Bi{sub 2}Te{sub 3} embedded MOS structures are very interesting for memory application.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2017

Method of making dielectric capacitors with increased dielectric breakdown strength

The invention is directed to a process for making a dielectric ceramic film capacitor and the ceramic dielectric laminated capacitor formed therefrom, the dielectric ceramic film capacitors having increased dielectric breakdown strength. The invention increases breakdown strength by embedding a conductive oxide layer between electrode layers within the dielectric layer of the capacitors. The conductive oxide layer redistributes and dissipates charge, thus mitigating charge concentration and micro fractures formed within the dielectric by electric fields.

36 MATERIALS SCIENCE↗
DOE OSTI2015

Miniature lowpass filters in low loss 9k7 LTCC

DuPont 9k7 low temperature cofired ceramic (LTCC) is a low loss, or high quality factor Q, tape system targeting at radio frequency (RF) applications. This paper reports the effect of a critical process parameter, heating rate, on the densification and dielectric properties of the 9k7 LTCC. The role of competing densification and crystallization during the sintering of 9k7 is discussed. The high Q of DuPont 9K7 can be used to improve RF system performance, for example a better receiver noise figure, by designing embedded passive RF components such as inductors, capacitors and filters. As a result, miniaturized multilayer low pass filters (LPF) with a wide stopband were fabricated to showcase the technology.

36 MATERIALS SCIENCE↗
DOE OSTI2015

Miniature low-pass filter in low-loss 9k7 LTCC

DuPont 9k7 low-temperature cofired ceramic (LTCC) is a low-loss, or high-quality-factor Q, tape system targeting at radio frequency (RF) applications. This paper reports on the effect of a critical process parameter, the heating rate, on the densification and dielectric properties of the 9k7 LTCC. The role of competing densification and crystallization during the sintering of 9k7 is discussed. The high Q of DuPont 9K7 can be used to improve RF system performance, for example a better receiver noise figure, by designing embedded passive RF components such as inductors, capacitors and filters. Furthermore, miniaturized multilayer low-pass filters (LPF) with a wide stopband were fabricated to showcase the technology.

36 MATERIALS SCIENCE↗