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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Information Leakage Analysis using a Co-design-Based Fault Injection Technique on a RISC-V Microprocessor

The RISC-V instruction set architecture open licensing policy has spawned a hive of development activity, making a range of implementations publicly available. The environments in which RISC-V operates have expanded correspondingly, driving the need for a generalized approach to evaluating the reliability of RISC-V implementations under adverse operating conditions or after normal wear-out periods. Fault injection (FI) refers to the process of changing the state of registers or wires, either permanently or momentarily, and then observing execution behavior. The analysis provides insight into the development of countermeasures that protect against the leakage or corruption of sensitive information which might occur because of unexpected execution behavior. In this paper, we develop a hardware-software co-design architecture that enables fast, configurable fault emulation and utilize it for information leakage and data corruption analysis. Modern System-on-chip FPGAs enable building an evaluation platform where control elements run on a processor(s) (PS) simultaneously with the target design running in the programmable logic (PL). Software components of the FI system introduce faults and report execution behavior. A pair of RISC-V FI-instrumented implementations are created and configured to execute the Advanced Encryption Standard and Twister algorithms. Key and plaintext information leakage and degraded pseudo-random sequences are both observed in the output for a subset of the emulated faults.

42 ENGINEERING↗
DOE OSTI2025

Machine learning for photovoltaic single axis tracker fault detection and classification

More than 81% of the annual capacity of utility-scale photovoltaic (PV) power plants in the U.S. use single-axis trackers (SATs) due to SATs delivering 4% in capacity factor on average over fixed-array systems. However, SATs are subject to faults, such as software misconfigurations and mechanical failures, resulting in suboptimal tracking. If left undetected, the overall power yield of the PV power plant is reduced significantly. Minimizing downtime and ensuring efficient operation of SATs requires robust detection and diagnosis mechanisms for SAT faults. We present a machine learning framework for implementing real-time SAT fault detection and classification. Our implementation of the proposed framework reliably identifies measurements taken from a test PV system undergoing emulated SAT faults relative to state-of-the-art algorithms and produces nearly zero false positives on our testing days. Code and data are available at https://pvpmc.sandia.gov/tools.

Fault classification↗
DOE OSTI2024

Emulation and detection of physical faults and cyber-attacks on building energy systems through real-time hardware-in-the-loop experiments

The increasing use of remote or mobile access, integrated wearable technologies, data exchange, and cloud-based data analytics in modern smart buildings is steering the building industry towards open communication technologies. The increased connectivity and accessibility could lead to more cyber-attacks in smart buildings. On the other hand, physical faults (e.g., HVAC -heating, ventilation, and air-conditioning faults) may have similar adverse impacts as those from the cyber-attacks on building energy systems, such as occupant discomfort, energy wastage, and equipment downtime. However, current physical behavior-based anomaly detection methods fail to differentiate between cyber-attacks and physical faults in building energy systems. Moreover, the challenge in collecting real-world threat data with ground truth has led researchers to rely on numerical models with user-defined assumptions, which may not accurately reflect real-world conditions due to the lack of in-situ experimental datasets. To address these challenges and gaps, this paper presents a flexible hardware-in-the-loop (HIL) testbed for generating cyber-attack and physical fault datasets and demonstrating threat detection algorithms in a real building automation system (BAS) environment. This testbed combines hardware (i.e., real BAS with local HVAC controllers and a physical network) with software (i.e., high-fidelity models to represent behaviors of building envelope and HVAC energy systems), enabling emulations of realistic threats. Five HIL experiments, including one baseline without any threats, two with physical faults, and two with cyber-attacks, were conducted to generate datasets containing detailed network traffic and system states. A joint classification framework, incorporating a network analyzer and a physical HVAC fault detector, was proposed to automatically detect cyber-physical abnormalities on BAS at both the network and the physical HVAC levels. The network analyzer comprises a conditional random fields (CRF) based command validator and a statistics-based detection strategy. The fault detector employs a weather and schedule-based pattern matching and feature-based principal component analysis (WPM-FPCA) method. Evaluation of the classification using four metrics from the multi-class confusion matrix revealed an average accuracy of 90.2%, recall of 89.7%, precision of 88.5% and F1-score of 89.2%. Finally, these results demonstrate that the proposed joint classification framework can effectively differentiate between specific types of cyber-attacks (e.g., device reinitialization attack, network Denial-of-Service attack) and physical faults (e.g., air handling unit operational fault, cooling coil valve stuck) in real time for improved building energy management.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2024

An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

Recent evaluations of counter-based periodic testing strategies for fault detection in Microprocessor (μP) have shown that only a small set of counters is needed to provide complete coverage of severe faults. Severe faults are defined as faults that leak sensitive information, e.g., an encryption key on the output of a serial port. Alternatively, fault detection can be accomplished by executing instructions that periodically test the control and functional units of the μP. In this paper, we propose a fault detection method that utilizes an ’engineered’ executable program combined with a small set of strategically placed counters in pursuit of a hardware Periodic Built-In-Self-Test (PBIST). We analyze two distinct methods for generating such a binary; the first uses an Automatic Test Generation Pattern (ATPG)-based methodology, and the second uses a process whereby existing counter-based node-monitoring infrastructure is utilized. We show that complete fault coverage of all leakage faults is possible using relatively small binaries with low latency to fault detection and by utilizing only a few strategically placed counters in the μP.

42 ENGINEERING↗
DOE OSTI2026

A Systematic Framework for Tuning Open-Source Multifunctional IBR Models To Emulate OEM Black-Box Fault Dynamics

This paper presents a systematic framework to tune a generic IBR EMT model to match with an OEM provided balckbox inverter model based on the fault current responses. The key learnings and findings are summarized as follows: The tunable key parameters include inner control loops and current limiters to align the fault current magnitude, sequence content, and phase trajectories with the OEM models across diverse fault type and locations. The tuned model's fidelity is validated through comparative analysis with an OEM blackbox model, assessing both the fault current response and the responses of multiple relay elements. The results demonstrate the tuned generic model can trigger relay decision logic that is identical or near identical to that of the OEM model, thus generating very good match model for fault studies.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2025

Nuclear Thermal Rocket Emulator for a Hardware-in-the-Loop Test Bed

To support NASA’s mission to use nuclear thermal rockets for future Mars missions, an instrumentation and control test bed has been built at Oak Ridge National Laboratory. The system is designed as a hardware-in-the-loop test bed for testing control elements and autonomous control algorithms for nuclear thermal propulsion rockets. The mock reactor system consists of a modular and scalable framework, using inexpensive components and open-source software. The hardware system consists of a two-phase flow loop and a mock reactor with six control drums. A single-board computer (NVIDIA Jetson) handles reactor core emulation and hosts a message queuing telemetry transport broker that allows user-deployed control algorithms to interact with the system hardware. The reactor emulator receives sensor data from the hardware and provides the simulated performance of the reactor under steady-state, transient, and fault conditions. The emulator uses a reactivity lookup table and the point kinetics equations to solve for the reactor dynamics in real time. Emulated reactor dynamics and sensor input inform the autonomous control algorithm’s decision-making in a closed-loop manner. The current system is capable of operating at 10 Hz, but faster cycle rates are an area of ongoing research. This test bed will enable NASA and other space vendors to rigorously test their autonomous control systems for NTP rockets under transient (reactor startup and shutdown), steady-state, and fault conditions to reduce development time and risk for autonomous control systems in future missions.

autonomous control↗
DOE OSTI2026

An efficient explicit implementation of a near-optimal quantum algorithm for simulating linear dissipative differential equations

We propose an efficient block-encoding technique for the implementation of the Linear Combination of Hamiltonian Simulations (LCHS) for simulating dissipative initial-value problems. This algorithm approximates a target nonunitary operator as a weighted sum of Hamiltonian evolutions, thereby emulating a dissipative problem by mixing various time scales. We introduce an efficient encoding of the LCHS into a quantum circuit based on a simple coordinate transformation that turns the dependence on the summation index into a trigonometric function. Classically, this method is equivalent to the use of a highly accurate Fejér-Clenshaw-Curtis quadrature formula. Quantumly, this significantly simplifies block-encoding of a dissipative problem and allows one to perform an exponential number of Hamiltonian simulations by a single Quantum Signal Processing (QSP) circuit. The resulting LCHS circuit has high success probability and the selector scales logarithmically with the number of terms in the LCHS sum and linearly with time. Careful analysis of error convergence proves that this method is more efficient than other LCHS circuits that have recently appeared in the literature. We verify the quantum circuit and its scaling by simulating it on a digital emulator of fault-tolerant quantum computers and, as a test problem, solve the advection-diffusion equation. The proposed algorithm can be used for simulating a wide class of nonunitary initial-value problems including the Liouville equation with added dissipation and linear embeddings of nonlinear systems, such as the Koopman-von Neumann and Carleman embeddings.

Novikau, I [Lawrence Livermore National Laboratory↗
DOE OSTI2025

Logical error rates for the surface code under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions

With fault-tolerant quantum computing (FTQC) on the horizon, it is critical to understand sources of logical errors in plausible hardware implementations of quantum error-correcting codes. Detailed error modeling of computational instructions on particular FTQC architectures will enable the better prediction of error propagation in FT-encoded quantum circuits while revealing where greater attention is needed in hardware design. In this work, we consider logical error rates for the surface code implemented on a hypothetical grid-based trapped-ion quantum charge-coupled device architecture. Specifically, we construct logical channels for the idling surface code and examine its diamond error under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions. We include the coherent dephasing noise that is known to accumulate during physical qubit idling and transport in these systems, determining idling and transport durations using the time-resolved output of an open-source trapped-ion surface code compiler. To estimate expectation values of logical Pauli observables following hardware circuits containing non-Clifford sources of noise, we utilize a Monte Carlo technique to sample from an underlying quasiprobability distribution of Clifford circuits that we independently simulate in a phase-sensitive fashion. We verify error suppression up to code distance 𝑑 = 11 at coherent dephasing rates near and below those of current-generation trapped-ion quantum computers and find that logical error rates align with those of analogous fully stochastic simulations in this regime. Exploring higher dephasing rates at 𝑑 = 3−5, we find evidence for growing coherent rotations about all three logical Pauli axes, increased diagonal logical error process matrix elements relative to those of stochastic simulations, and a reduced dephasing rate threshold. Overall, our work paves a way toward realistic hardware emulation of small fault-tolerant quantum processes, e.g., members of an FTQC instruction set.

Quantum benchmarking↗
DOE OSTI2024

A hardware-in-the-loop (HIL) testbed for cyber-physical energy systems in smart commercial buildings

In recent years, there has been a growing trend toward the development of smart buildings that rely on cyber-physical systems (CPS) to optimize occupant comfort, safety, and energy efficiency. To ensure the reliable and efficient operation of CPS with designed control strategies, it is important to evaluate their performance under various scenarios before deploying them in the real world. This is where a Hardware-in-the-loop (HIL) testbed designed for studying sensor and control-related studies in smart buildings can be highly valuable. With the growing threat of cyber-attacks and physical faults targeting smart buildings, it is essential to ensure the security of building operations. A HIL testbed can emulate cyber-attack and physical fault scenarios, allowing researchers to develop and test threat detection and mitigation algorithms. This enables researchers to identify potential issues and optimize the algorithms in a safe and controlled environment before they are deployed in real-world settings, reducing the risk of failures that can negatively impact occupant comfort, safety, and energy efficiency. Therefore, this paper developed a HIL testbed designed for cyber-physical energy systems (e.g. buildings automation system (BAS)) in smart commercial buildings. The HIL testbed is comprised of a real-time building and Heating, Ventilation, and Air-Conditioning (HVAC) emulator using Modelica-based dynamic models, a set of BAS controllers, and a BAS computer server. The data generation capability of the HIL testbed is demonstrated by tracking normal and faulty operating data in the BAS, as well as monitoring detailed network traffic in the local BAS network. Here, this study further demonstrates the HIL testbed’s capability by conducting case studies on real-time physical fault and cyber-attack experiments using a Department of Energy (DOE) prototype commercial building. It is anticipated that the fully functional HIL testbed will be utilized for a variety of sensor and control-related studies, including but not limited to testing, developing, validating of different HVAC control strategies, fault detection & diagnosis, energy monitoring and analysis, cyber security study, etc.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2022

Multi phenomena melt pool sensor data fusion for enhanced process monitoring of laser powder bed fusion additive manufacturing

Finding actionable trends in laser-based metal additive manufacturing process monitoring data is challenging owing to the diversity and complexity of the underlying physical interactions. A single monitoring solution that captures a particular process phenomenon, such as a photodiode that tracks melt pool intensity, is not alone capable of evaluating process stability or detecting flaw formation with sufficient precision for routine application in industry. In this work, to improve flaw detection performance, we adopted a data fusion approach that captures multiple process phenomena. To demonstrate this, we acquired data from laser powder bed fusion (LPBF) builds of cylindrical specimens produced with different laser spot sizes, emulating defocusing due to process faults such as thermal lensing. The resulting specimens had porosity of varying types and severity, quantified by post-build non-destructive X-ray computed tomography, Archimedes density measurements, and destructive metallographic characterization. During the build, the melt pool state was monitored with two coaxial high-speed video cameras and a temperature field imaging system. Physically intuitive low-level melt pool signatures, such as melt pool temperature, shape and size, and spatter intensity were extracted from this high-dimensional, image-based sensor data. These process signatures were subsequently used as input features in relatively simple machine learning models, such as a support vector machine, which were trained to detect laser defocusing, and in addition, predict porosity type and severity. The results show that the data fusion approach significantly enhanced system performance by reducing the overall false positive rate from ~ 0.1 to ~ 0.001 without sacrificing the true positive rate (~0.90). These results were at par with a black-box, deep machine learning approach (convolutional neural network).

36 MATERIALS SCIENCE↗
DOE OSTI2024

Robust Disturbance Rejection Rotor Current Control of Doubly-Fed Induction Generators

This article proposes a robust transient disturbance rejection current controller (TDRCC) to improve the transient performance of doubly-fed induction generators (DFIGs) in wind turbines during grid disturbances, such as short circuits. Here, the proposed robust TDRCC replaces the proportional-integral-derivative (PID) current controllers conventionally used in the vector control scheme of the DFIG rotor side converter (RSC). The TDRCC estimates the transient disturbances caused by grid faults or other external disturbances and provides compensation to the DFIG rotor voltage in the current control loops of the RSC to improve the robustness of the controller to disturbance. A sliding-mode current controller (SMCC) is also designed to highlight the transient performance improvement of the DFIG using the TDRCC over the state-of-the-art control methods during grid short circuit faults. Simulation studies are conducted in PSCAD/EMTDC for a 3.6-MW DFIG wind turbine with the proposed TDRCC, the conventional PI controller, and the SMCC, respectively during the most severe balanced three-phase grid short circuit fault specified by the U.S. grid code as well as an unbalance single-phase grid short circuit fault. Hardware experiments are conducted on a 200-W DFIG wind turbine emulator with the three different controllers for the same three-phase short circuit fault. Simulation and hardware experiment results show that the TDRCC reduces the peak rotor current significantly when compared with the PI and SMCC controlled DFIG system and, therefore, would help prolong the lifespan of the DFIG's power electronics and reduce maintenance costs.

42 ENGINEERING↗
DOE OSTI2022

Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor

Advanced, superscalar microprocessors (μP) are highly susceptible to wear-out failures because of their highly complex, densely packed circuit structure and extreme operational frequencies. Although many types of fault detection and mitigation strategies have been proposed, none have addressed the specific problem of detecting faults that lead to information leakage events on I/O channels of the μP. Information leakage can be defined very generally as any type of output that the executing program did not intend to produce. In this work, we restrict this definition to output that represents a security concern, and in particular, to the leakage of plaintext or encryption keys, and propose a counter-based countermeasure to detect faults that cause this type of leakage event. Fault injection (FI) experiments are carried out on two RISC-V microprocessors emulated as soft cores on a Xilinx multi-processor System-on-chip (MPSoC) FPGA. The μP designs are instrumented with a set of counters that records the number of transitions that occur on internal nodes. The transition counts are collected from all internal nodes under both fault-free and faulty conditions, and are analyzed to determine which counters provide the highest fault coverage and lowest latency for detecting leakage faults. We show that complete coverage of all leakage faults is possible using only a single counter strategically placed within the branch compare logic of the μPs.

42 ENGINEERING↗
DOE OSTI2023

Validation of the Fault Ride-Through Response of a Generic EMT Inverter Model by Laboratory Testing

This paper presents the validation of the fault ride-through response of a large-scale inverter model using laboratory testing of a commercial inverter. First, we present the generic inverter model specifications. The generic inverter control is developed based on the fault ride-through response performance requirements of IEEE Std 2800-2022 for inverter-based resources. Next, we present laboratory tests that emulate voltages at the inverter terminal resulting from balanced and unbalanced faults on the transmission system. The tests are performed on a commercia12.2 MVA battery storage inverter at the U.S. National Renewable Energy Laboratory. Comparisons of the model's response to the laboratory measurements show the generic model presented can predict the controlled response of the commercial equipment. The differences between the model's response and the laboratory measurements during the initial transient at fault inception are discussed.

fault ride-through↗
DOE OSTI2024

Adaptive Fault Current-Limiting Control of MMC for Protection of Multiterminal HVDC Systems: Preprint

For the development of multi-terminal high voltage DC (MTDC) transmission, it is critical to design the protection system that can selectively isolate the faulty area from the healthy part of the dc grid using DC circuit breakers (DCCBs) while ensuring continuous operation of converter stations in the healthy part. However, because of the lack of fault current blocking capability in half-bridge (HB) modular multilevel converters (MMCs), when a dc fault occurs, the rising fault currents can quickly reach the blocking threshold within a few milliseconds and disrupt the operation of MMCs in the healthy part. Large DC reactors are often considered in series with DCCBs to reduce the rate of rise of fault currents and prevent blocking of MMCs in the healthy part of the grid. However, large DC reactors can prohibitively increase the cost of the system, particularly when they are considered in an offshore environment, for instance in offshore wind projects. Large dc reactors can also introduce stability issues and create post-fault oscillations. This paper presents an adaptive fault current limiting control method for MMCs to avoid their blocking and enable continuous operation of MTDC systems. It contains two parts: The first part is based on circulating current feedforward control that emulates virtual reactors in each arm of an MMC, which is immediately activated when the fault current starts to increase, to reduce the rate of rise of the fault current; the second part is triggered when the fault current exceeds a preset threshold by temporarily bypassing the SMs, serving as a complement to the fault current limiting effect of the first part. Both parts do not require fault detection signal and they are activated automatically during faults. Simulation case studies of a four-terminal bipolar MMC-HVDC system are presented to demonstrate the effectiveness of the proposed control methods.

active fault current limiting↗
DOE OSTI2024

Adaptive Fault Current-Limiting Control of MMC for Protection of Multiterminal HVDC Systems

A crucial requirement of the protection system for multi-terminal high-voltage DC (MTDC) transmission is that it is capable of selectively isolating the faulty area from the healthy part of the network using DC circuit breakers (DCCBs), while ensuring continuous operation of converter stations in the healthy part of the network. But in the half-bridge modular multilevel converters (HB-MMCs) based MTDC system, since HB-MMCs do not have fault current absorption capability, when a DC fault occurs, the rising fault currents can quickly reach the blocking threshold within a few milliseconds and disrupt the operation of the MMCs in the healthy part. To facilitate fault-ride-through capability of MTDC system, large DC reactors are often considered in series with DCCBs to reduce the rate of rise of the fault current and prevent blocking the MMCs in the healthy part of the DC networks; however, large DC reactors prohibitively increase the cost of the system, introduce stability issues and can create post-fault oscillations. This paper presents an adaptive fault current-limiting control method for MMCs to avoid their blocking and enable the continuous operation of the healthy part of MTDC systems. The method contains two parts: The first part is based on circulating current feedforward control, which emulates virtual reactors in each arm of an MMC, and is immediately activated when the fault current starts to increase to reduce the rate of rise of the fault current. The second part temporarily bypasses all the submodules when the fault current exceeds a preset threshold, complementing the fault current-limiting effect of the first part. Neither part requires fault detection signals, and they are automatically activated during faults. Simulation case studies of a four-terminal bipolar MMC-based high-voltage DC system are presented to demonstrate the effectiveness of the proposed control methods.

active fault current limiting↗