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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Dynamic, symmetry-preserving, and hardware-adaptable circuits for quantum computing many-body states and correlators of the Anderson impurity model

We present a hardware-reconfigurable ansatz on N q -qubits for the variational preparation of many-body states of the Anderson impurity model (AIM) with N imp + N bath = N q /2 sites, which conserves total charge and spin z component within each variational search subspace. The many-body ground state of the AIM is determined as the minimum over all minima of O(N$^2_ q$) distinct charge-spin sectors. Hamiltonian expectation values are shown to require ω(N q ) < N meas. $\leqslant$ O(N imp N bath ) symmetry-preserving, parallelizable measurement circuits, each amenable to postselection. To obtain the one-particle impurity Green’s function we show how initial Krylov vectors can be computed via midcircuit measurement and how Lanczos iterations can be computed using the symmetry-preserving ansatz. For a single-impurity Anderson model with a number of bath sites increasing from one to seven, we show using numerical emulation that the ease of variational ground-state preparation is suggestive of linear scaling in circuit depth and subquartic scaling in optimizer complexity. We therefore expect that, combined with time-dependent methods for Green’s function computation, our ansatz provides a useful tool to account for electronic correlations on early fault-tolerant processors. Finally, with a view towards computing real materials properties of interest like magnetic susceptibilities and electron-hole propagators, we provide a straightforward method to compute many-body, time-dependent correlation functions using a combination of time evolution, midcircuit measurement-conditioned operations, and the Hadamard test.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Precision Tomography of a Three-Qubit Donor Quantum Processor in Silicon

Nuclear spins were among the first physical platforms to be considered for quantum information processing, because of their exceptional quantum coherence and atomic-scale footprint. However, their full potential for quantum computing has not yet been realized, owing to the lack of methods with which to link nuclear qubits within a scalable device combined with multi-qubit operations with sufficient fidelity to sustain fault-tolerant quantum computation. Here we demonstrate universal quantum logic operations using a pair of ion-implanted 31 P donor nuclei in a silicon nanoelectronic device. A nuclear two-qubit controlled-Z gate is obtained by imparting a geometric phase to a shared electron spin, and used to prepare entangled Bell states with fidelities up to 94.2(2.7)%. The quantum operations are precisely characterized using gate set tomography (GST), yielding one-qubit average gate fidelities up to 99.95(2)%, two-qubit average gate fidelity of 99.37(11)% and two-qubit preparation/measurement fidelities of 98.95(4)%. These three metrics indicate that nuclear spins in silicon are approaching the performance demanded in fault-tolerant quantum processors. We then demonstrate entanglement between the two nuclei and the shared electron by producing a Greenberger-Horne-Zeilinger three-qubit state with 92.5(1.0)% fidelity. Because electron spin qubits in semiconductors can be further coupled to other electrons or physically shuttled across different locations, these results establish a viable route for scalable quantum information processing using donor nuclear and electron spins.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2020

Noisy Intermediate-Scale Quantum Applications on a Pathfinder System

Work performed under this one-year LDRD was concerned with estimating resource requirements for small quantum test beds that are expected to be available in the near future. This work represents a preliminary demonstration of our ability to leverage quantum hardware for solving small quantum simulation problems in areas of interest to the DOE. The algorithms enabling such studies are hybrid quantum-classical variational algorithms, in particular the widely-used variational quantum eigensolver (VQE). Employing this hybrid algorithm, in which the quantum computer complements the classical one, we implemented an end-to-end application-level toolchain that allows the user to specify a molecule of interest and compute the ground state energy using the VQE approach. We found significant limitations attributable to the classical portion of the hybrid system, including a greater than greater-than-quartic power scaling of the classical memory requirements with the system size. Current VQE approaches would require an exascale machine for solving any molecule with size greater than 150 nuclei. Our findings include several improvements that we implemented into the VQE toolchain, including a new classical optimizer that is decades old but hadn't been considered before in the VQE ecosystem. Our findings suggest limitations to variational hybrid approaches to simulation that further motivate the need for a gate-based fault-tolerant quantum processor that can implement larger problems using the fully digital quantum phase estimation algorithm.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Benchmarking quantum logic operations relative to thresholds for fault tolerance

Contemporary methods for benchmarking noisy quantum processors typically measure average error rates or process infidelities. However, thresholds for fault-tolerant quantum error correction are given in terms of worst-case error rates—defined via the diamond norm—which can differ from average error rates by orders of magnitude. One method for resolving this discrepancy is to randomize the physical implementation of quantum gates, using techniques like randomized compiling (RC). In this work, we use gate set tomography to perform precision characterization of a set of two-qubit logic gates to study RC on a superconducting quantum processor. We find that, under RC, gate errors are accurately described by a stochastic Pauli noise model without coherent errors, and that spatially correlated coherent errors and non-Markovian errors are strongly suppressed. We further show that the average and worst-case error rates are equal for randomly compiled gates, and measure a maximum worst-case error of 0.0197(3) for our gate set. Our results show that randomized benchmarks are a viable route to both verifying that a quantum processor’s error rates are below a fault-tolerance threshold, and to bounding the failure rates of near-term algorithms, if—and only if—gates are implemented via randomization methods which tailor noise.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Offset Charge Dependence of Measurement-Induced Transitions in Transmons

A key challenge in achieving scalable fault tolerance in superconducting quantum processors is readout fidelity, which lags behind one- and two-qubit gate fidelity. A major limitation in improving qubit readout is measurement-induced transitions, also referred to as qubit ionization, caused by multiphoton qubit-resonator excitation occurring at specific photon numbers. Since ionization can involve highly excited states, it has been predicted that in transmons—the most widely used superconducting qubit—the photon number at which measurement-induced transitions occur is gate-charge dependent. This dependence is expected to persist deep in the transmon regime where the qubit frequency is gate-charge insensitive. We experimentally confirm this prediction by characterizing measurement-induced transitions with increasing resonator photon population while actively calibrating the transmon’s gate charge. Furthermore, because highly excited states are involved, achieving quantitative agreement between theory and experiment requires accounting for higher-order harmonics in the transmon Hamiltonian.

Quantum circuits↗
DOE OSTI2023

Evidence for the utility of quantum computing before fault tolerance

Quantum computing promises to offer substantial speed-ups over its classical counterpart for certain problems. However, the greatest impediment to realizing its full potential is noise that is inherent to these systems. The widely accepted solution to this challenge is the implementation of fault-tolerant quantum circuits, which is out of reach for current processors. Here we report experiments on a noisy 127-qubit processor and demonstrate the measurement of accurate expectation values for circuit volumes at a scale beyond brute-force classical computation. We argue that this represents evidence for the utility of quantum computing in a pre-fault-tolerant era. These experimental results are enabled by advances in the coherence and calibration of a superconducting processor at this scale and the ability to characterize and controllably manipulate noise across such a large device. We establish the accuracy of the measured expectation values by comparing them with the output of exactly verifiable circuits. In the regime of strong entanglement, the quantum computer provides correct results for which leading classical approximations such as pure-state-based 1D (matrix product states, MPS) and 2D (isometric tensor network states, isoTNS) tensor network methods break down. These experiments demonstrate a foundational tool for the realization of near-term quantum applications.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2026

A cryogenic muon tagging system based on kinetic inductance detectors for superconducting quantum processors

Ionizing radiation has emerged as a potential limiting factor for superconducting quantum processors, inducing quasiparticle bursts and correlated errors that challenge fault-tolerant operation. Atmospheric muons are particularly problematic due to their high energy and penetration power, making passive shielding ineffective. Therefore, monitoring the real-time muon flux is crucial to guide the development of alternative error-correction or mitigation strategies. We present the design, simulation, and first operation of a cryogenic muon-tagging system based on kinetic inductance detectors (KIDs), developed as a stand-alone cryogenic particle-tagging module for superconducting quantum processors. The system consists of two KIDs arranged in a vertical stack and operated at ∼20 mK. Monte Carlo simulations based on Geant4 guided the prototype design and provided reference expectations for muon-tagging efficiency and accidental coincidences due to ambient γ-rays. We observed a muon-induced coincidence rate among the top and bottom detectors of (192 ± 9) $\times\,10^{-3}$ events s$^{−1}$, in excellent agreement with the Monte Carlo prediction. The prototype achieves a muon-tagging efficiency of about 90% with negligible dead time. These results demonstrate the feasibility of operating a muon-tagging system at millikelvin temperatures and represent a key step toward the integration of cryogenic veto systems with multi-qubit chips to mitigate muon-induced errors.

Mariani, Ambra [INFN, Rome] (ORCID:000000028184857↗
DOE OSTI2022

QSCOUT Progress Report, June 2022 [Quantum Scientific Computing Open User Testbed]

Quantum information processing has reached an inflection point, transitioning from proof-of-principle scientific experiments to small, noisy quantum processors. To accelerate this process and eventually move to fault-tolerant quantum computing, it is necessary to provide the scientific community with access to whitebox testbed systems. The Quantum Scientific Computing Open User Testbed (QSCOUT) provides scientists unique access to an innovative system to help advance quantum computing science.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Mid-circuit correction of correlated phase errors using an array of spectator qubits

Scaling up invariably error-prone quantum processors is a formidable challenge. Although quantum error correction ultimately promises fault-tolerant operation, the required qubit overhead and error thresholds are daunting. In a complementary proposal, colocated, auxiliary “spectator” qubits act as in situ probes of noise and enable real-time, coherent corrections of data qubit errors. We used an array of cesium spectator qubits to correct correlated phase errors on an array of rubidium data qubits. By combining in-sequence readout, data processing, and feedforward operations, these correlated errors were suppressed within the execution of the quantum circuit. The protocol is broadly applicable to quantum information platforms and establishes key tools for scaling neutral-atom quantum processors: mid-circuit readout of atom arrays, real-time processing and feedforward, and coherent mid-circuit reloading of atomic qubits.

Science & Technology - Other Topics↗
DOE OSTI2023

Shadow Distillation: Quantum Error Mitigation with Classical Shadows for Near-Term Quantum Processors

Mitigating errors in quantum information processing devices is especially important in the absence of fault tolerance. An effective method in suppressing state-preparation errors is using multiple copies to distill the ideal component from a noisy quantum state. Here, we use classical shadows and randomized measurements to circumvent the need for coherent access to multiple copies at an exponential cost. We study the scaling of resources using numerical simulations and find that the overhead is still favorable compared to full state tomography. We optimize measurement resources under realistic experimental constraints and apply our method to an experiment preparing a Greenberger-Horne-Zeilinger state with trapped ions. In addition to improving stabilizer measurements, the analysis of the improved results reveals the nature of errors affecting the experiment. Hence, our results provide a directly applicable method for mitigating errors in near-term quantum computers.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Modular Quantum Processor with an All-to-All Reconfigurable Router

Superconducting qubits provide a promising approach to large-scale fault-tolerant quantum computing. However, qubit connectivity on a planar surface is typically restricted to only a few neighboring qubits. Achieving longer-range and more flexible connectivity, which is particularly appealing in light of recent developments in error-correcting codes, however, usually involves complex multilayer packaging and external cabling, which is resource intensive and can impose fidelity limitations. Here, we propose and realize a high-speed on-chip quantum processor that supports reconfigurable all-to-all coupling with a large on-off ratio. We implement the design in a four-node quantum processor, built with a modular design comprising a wiring substrate coupled to two separate qubit-bearing substrates, each including two single-qubit nodes. We use this device to demonstrate reconfigurable controlled-𝑍 gates across all qubit pairs, with a benchmarked average fidelity of 96.00% ± 0.08% and best fidelity of 97.14% ± 0.07%, limited mainly by dephasing in the qubits. We also generate multiqubit entanglement, distributed across the separate modules, demonstrating GHZ-3 and GHZ-4 states with fidelities of 88.15% ± 0.24% and 75.18% ± 0.11%, respectively. This approach promises efficient scaling to larger-scale quantum circuits and offers a pathway for implementing quantum algorithms and error-correction schemes that benefit from enhanced qubit connectivity.

Quantum circuits↗
DOE OSTI2021

Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Furthermore, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop’s sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

42 ENGINEERING↗
DOE OSTI2025

Measuring error rates of mid-circuit measurements

High-fidelity mid-circuit measurements, which read out the state of specific qubits in a multiqubit processor without destroying them or disrupting their neighbors, are a critical component for useful quantum computing. They enable fault-tolerant quantum error correction, dynamic circuits, and other paths to solving classically intractable problems. But there are few methods to assess their performance comprehensively. In this work, we address this gap by introducing the first randomized benchmarking protocol that measures the rate at which mid-circuit measurements induce errors in many-qubit circuits. Using this protocol, we detect and eliminate previously undetected measurement-induced crosstalk in a 20-qubit trapped-ion quantum computer. Then, we use the same protocol to measure the rate of measurement-induced crosstalk error on a 27-qubit IBM Q processor, and quantify how much of that error is eliminated by dynamical decoupling.

Hothem, Daniel [Sandia National Laboratories (SNL-↗
DOE OSTI2025

Quantum Zeno Monte Carlo for computing observables

The recent development of logical quantum processors marks a pivotal transition from the noisy intermediate-scale quantum (NISQ) era to the fault-tolerant quantum computing (FTQC) era. These devices have the potential to address classically challenging problems with polynomial computational time using quantum properties. However, they remain susceptible to noise, necessitating noise resilient algorithms. We introduce Quantum Zeno Monte Carlo (QZMC), a classical-quantum hybrid algorithm that demonstrates resilience to device noise and Trotter errors while showing polynomial computational cost for a gapped system. QZMC computes static and dynamic properties without requiring initial state overlap or variational parameters, offering reduced quantum circuit depth.

Han, Mancheon [Korea Institute for Advanced Study ↗
DOE OSTI2020

Diagnosing and Destroying Non-Markovian Noise

Nearly every protocol used to analyze the performance of quantum information processors is based on an assumption that the errors experienced by the device during logical operations are constant in time and are insensitive to external contexts. This assumption is pervasive, rarely stated, and almost always wrong. Quantum devices that do behave this way are termed "Markovian:' but nearly every system we have ever probed has displayed drift or crosstalk or memory effects they are all non-Markovian. Strong non-Markovianity introduces spurious effects in characterization protocols and violates assumptions of the fault-tolerance threshold theorems. This SAND report details a three year laboratory-directed research and development (LDRD) project entitled, "Diagnosing and Destroying non-Markovian Noise in Quantum Information Processors." This program was initiated to build tools to study non-Markovian dynamics and quantum systems and develop robust methodologies for eliminating it. The program achieved a number of notable successes, including the first statistically rigorous protocol for identifying and characterizing drift in quantum systems, a formalism for modeling memory effects in quantum devices, and the successful suppression of drift in a Sandia trapped-ion quantum processor.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Logical quantum processor based on reconfigurable atom arrays

Suppressing errors is the central challenge for useful quantum computing, requiring quantum error correction (QEC) for large-scale processing. However, the overhead in the realization of error-corrected ‘logical’ qubits, in which information is encoded across many physical qubits for redundancy, poses substantial challenges to large-scale logical quantum computing. Here we report the realization of a programmable quantum processor based on encoded logical qubits operating with up to 280 physical qubits. Using logical-level control and a zoned architecture in reconfigurable neutral-atom arrays, our system combines high two-qubit gate fidelities, arbitrary connectivity, as well as fully programmable single-qubit rotations and mid-circuit readout. Operating this logical processor with various types of encoding, we demonstrate improvement of a two-qubit logic gate by scaling surface-code distance from d = 3 to d = 7, preparation of colour-code qubits with break-even fidelities, fault-tolerant creation of logical Greenberger–Horne–Zeilinger (GHZ) states and feedforward entanglement teleportation, as well as operation of 40 colour-code qubits. Finally, using 3D [[8,3,2]] code blocks, we realize computationally complex sampling circuits with up to 48 logical qubits entangled with hypercube connectivity with 228 logical two-qubit gates and 48 logical CCZ gates. We find that this logical encoding substantially improves algorithmic performance with error detection, outperforming physical-qubit fidelities at both cross-entropy benchmarking and quantum simulations of fast scrambling. These results herald the advent of early error-corrected quantum computation and chart a path towards large-scale logical processors.

74 ATOMIC AND MOLECULAR PHYSICS↗
DOE OSTI2024

Machine learning without a processor: Emergent learning in a nonlinear analog network

Standard deep learning algorithms require differentiating large nonlinear networks, a process that is slow and power-hungry. Electronic contrastive local learning networks (CLLNs) offer potentially fast, efficient, and fault-tolerant hardware for analog machine learning, but existing implementations are linear, severely limiting their capabilities. These systems differ significantly from artificial neural networks as well as the brain, so the feasibility and utility of incorporating nonlinear elements have not been explored. Here, we introduce a nonlinear CLLN—an analog electronic network made of self-adjusting nonlinear resistive elements based on transistors. We demonstrate that the system learns tasks unachievable in linear systems, including XOR (exclusive or) and nonlinear regression, without a computer. We find our decentralized system reduces modes of training error in order (mean, slope, curvature), similar to spectral bias in artificial neural networks. The circuitry is robust to damage, retrainable in seconds, and performs learned tasks in microseconds while dissipating only picojoules of energy across each transistor. This suggests enormous potential for fast, low-power computing in edge systems like sensors, robotic controllers, and medical devices, as well as manufacturability at scale for performing and studying emergent learning.

Science & Technology - Other Topics↗
DOE OSTI2023

Open Circuit Switch Fault Management Method of a Multi-Phase Synchronous Buck Converter for EV Charging Application

Multi-phase synchronous buck converter (MSBC) is becoming popular for the electric vehicle (EV) charging application because of its higher efficiency, smaller passive component sizes, bidirectional power flow, and output current ripple reduction through interleaving. This converter also provides higher reliability than the traditional single phase converter since its modular structure enables fault tolerant operation. Fault management in the converter requires the detection of switch fault, shut down of the faulty phase, and reconfiguration of the PWM signals for the healthy phases to avoid circulating current and high output current ripple. In addition, it is desirable that the fault management method can be implemented using the micro-controller unit (MCU) or digital signal processor (DSP), which are widely used to control power converters. This paper presents a fault management method for detecting switch faults and reconfiguring healthy phases using a DSP. The method is validated through simulations and experiments using a commercial off-the-shelf power stack.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗