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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Record high room temperature resistance switching in ferroelectric-gated Mott transistors unlocked by interfacial charge engineering

Abstract The superior size and power scaling potential of ferroelectric-gated Mott transistors makes them promising building blocks for developing energy-efficient memory and logic applications in the post-Moore’s Law era. The close to metallic carrier density in the Mott channel, however, imposes the bottleneck for achieving substantial field effect modulation via a solid-state gate. Previous studies have focused on optimizing the thickness, charge mobility, and carrier density of single-layer correlated channels, which have only led to moderate resistance switching at room temperature. Here, we report a record high nonvolatile resistance switching ratio of 38,440% at 300 K in a prototype Mott transistor consisting of a ferroelectric PbZr 0.2 Ti 0.8 O 3 gate and an R NiO 3 ( R : rare earth)/La 0.67 Sr 0.33 MnO 3 composite channel. The ultrathin La 0.67 Sr 0.33 MnO 3 buffer layer not only tailors the carrier density profile in R NiO 3 through interfacial charge transfer, as corroborated by first-principles calculations, but also provides an extended screening layer that reduces the depolarization effect in the ferroelectric gate. Our study points to an effective material strategy for the functional design of complex oxide heterointerfaces that harnesses the competing roles of charge in field effect screening and ferroelectric depolarization effects.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS2005

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

MacLeod, Todd C.↗
DOE OSTI2023

Nanoscale Ferroelectric Control of Novel Electronic States in Layered Two-Dimensional Materials (Final Report)

In this DOE Early Career project “Nanoscale Ferroelectric Control of Novel Electronic States in Layered Two-Dimensional Materials,” the PI’s group has combined ferroelectric field effect with nanoscale domain imaging and writing to design the electronic and optical properties of two-dimensional (2D) van der Waals materials, including graphene and transition metal dichalcogenides MoS2 and ReS2. The van der Waals materials have been prepared into field effect transistor (FET) devices with ferroelectric gates. Through domain patterning in a ferroelectric polymer PVDF-TrEF top-gate via conductive atomic force microscopy, the team has created programmable Schottky junctions in monolayer MoS 2 , where both barrier height and I-V rectifying polarity can be reconfigured. The transport anisotropy of monolayer to few-layer ReS 2 has been mapped out by defining the entire channel into an insulating state and creating nanoscale conducting paths along different directions through domain writing in the ferroelectric top-gate. The result shows that the conductivity along and perpendicular to the Re-chain can differ by >5.5x10 4 . Theoretical modeling points to the band origin of the transport anomaly and reveals the emergence of a flat band in few-layer ReS 2 . The interfacial epitaxial relation between ReS 2 and PVDF-TrFE further promotes the formation of close-packed, highly ordered PVDF-TrFE nanowires with width of 35 nm and 10 nm. Nonvolatile modulation of quantum Hall effect has been achieved in graphene FETs with a ferroelectric oxide Ba 0.4 Sr 0.6 TiO 3 back-gate. Scattering from the remote surface optical phonon in Ba 0.4 Sr 0.6 TiO 3 limits the room temperature mobility of graphene to be about 3x10 4 cm 2 /Vs. Steep-slope switching has been achieved in MoS 2 FETs back-gated by polycrystalline Pb(Zr,Ti)O 3 , which signals a static-state negative capacitance mode without involving an additional dielectric layer. Piezoresponse force microscopy studies show that the sub-threshold swing can be well correlated with the domain wall density in Pb(Zr,Ti)O 3 . The team also observes an unconventional filtering effect of the second harmonic generation response at the MoS 2 /Pb(Zr,Ti)O 3 heterointerface, which can be accounted for by the alignment between one of the polar axes of MoS 2 and the chiral dipole rotation at the surface of domain wall in Pb(Zr,Ti)O 3 . The research supported by this DOE grant has significantly advanced the fundamental understanding and functional design of ferroelectric/2D van der Waals heterostructures for their implementation towards energy applications.

36 MATERIALS SCIENCE↗
NASA NTRS2003

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

MacLeod, Todd C.↗
DOE OSTI2023

Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications

In this study, a compact and novel ferroelectric (FE) programmable majority gate is proposed and its novel application in Binary Neural Network (BNNs) is investigated. We demonstrate: i) by integrating N metal-ferroelectric-metal (MFM) capacitors on the gate of a transistor (1T-N-MFM structure), a nonvolatile and programmable majority (MAJ) gate that performs MAJ of AND between the gate input and polarization is realized; ii) validation the functionality of our 3-input MAJ of AND gate through comprehensive theoretical and experimental investigations; iii) a compact implementation of 3-input MAJ of XNOR gate that leverages only five of our 3-input MAJ of AND gates connected in parallel; iv) application of MAJ of XNOR gates to replace the XNOR gates and the first layer of the adder tree in the BNNs for up to 21x area saving on top of eliminating the energy-hungry memory accesses due to the compute-in-memory nature.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Phase diagrams and polarization reversal in nanosized Hf x Zr 1–x O 2–y

To describe the polar properties of nanosized Hf x Zr 1–x O 2–y , we evolve the “effective” Landau–Ginzburg–Devonshire (LGD) model based on the parametrization of the Landau expansion coefficients for polar and antipolar orderings. We have shown that the effective LGD model can predict the influence of screening conditions and size effects on phase diagrams, polarization reversal, and structural properties of nanosized Hf x Zr 1–x O 2–y of various shapes and sizes. To verify the model, we use the available experimental results for Hf x Zr 1–x O 2 thin films and oxygen-deficient HfO2–y nanoparticles prepared under different annealing conditions. X-ray diffraction, which was used to determine the phase composition of the HfO 2–y nanoparticles, revealed the formation of a ferroelectric orthorhombic phase in them. Micro-Raman spectroscopy was used to explore the correlation of lattice dynamics and structural changes that depend on the oxygen vacancy concentration in the HfO 2–y nanoparticles. Since our approach allows us to determine the conditions (shape, sizes, Zr content, and/or oxygen vacancy amount) for which nanosized Hf x Zr 1–x O 2–y are ferroelectric or antiferroelectric, we hope that the obtained results are useful for creation of next generation Si-compatible ferroelectric gate oxide nanomaterials.

36 MATERIALS SCIENCE↗
NASA NTRS2011

Characterization of a Common-Gate Amplifier Using Ferroelectric Transistors

In this paper, the empirical data collected through experiments performed using a FeFET in the common-gate amplifier circuit is presented. The FeFET common-gate amplifier was characterized by varying all parameters in the circuit, such as load resistance, biasing of the transistor, and input voltages. Due to the polarization of the ferroelectric layer, the particular behavior of the FeFET common-gate amplifier presents interesting results. Furthermore, the differences between a FeFET common-gate amplifier and a MOSFET common-gate amplifier are examined.

Hunt, Mitchell↗
NASA NTRS2009

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Phillips, Thomas A.↗
NASA NTRS2013

Mathematical Models of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field effect Transistor

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

Hunt, Mitchell↗
NASA NTRS2013

Extended Characterization of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

Hunt, Mitchell↗
NASA NTRS2006

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Phillips, Thomas A.↗
NASA NTRS2005

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Phillips, Thomas A.↗
NASA NTRS1999

I-V Characteristics of a Ferroelectric Field Effect Transistor

There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.

MacLeod, Todd C.↗
NASA NTRS2004

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

Phillips, Thomas A.↗
NASA NTRS2004

Ferroelectric Field Effect Transistor Model Using Partitioned Ferroelectric Layer and Partial Polarization

A model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. The model is based on an existing model that incorporates partitioning of the ferroelectric layer to calculate the polarization within the ferroelectric material. The model incorporates several new aspects that are useful to the user. It takes into account the effect of a non-saturating gate voltage only partially polarizing the ferroelectric material based on the existing remnant polarization. The model also incorporates the decay of the remnant polarization based on the time history of the FFET. A gate pulse of a specific voltage; will not put the ferroelectric material into a single amount of polarization for that voltage, but instead vary with previous state of the material and the time since the last change to the gate voltage. The model also utilizes data from FFETs made from different types of ferroelectric materials to allow the user just to input the material being used and not recreate the entire model. The model also allows the user to input the quality of the ferroelectric material being used. The ferroelectric material quality can go from a theoretical perfect material with little loss and no decay to a less than perfect material with remnant losses and decay. This model is designed to be used by people who need to predict the external characteristics of a FFET before the time and expense of design and fabrication. It also allows the parametric evaluation of quality of the ferroelectric film on the overall performance of the transistor.

MacLeod, Todd C.↗
NASA NTRS2010

Static Characteristics of the Ferroelectric Transistor Inverter

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

Mitchell, Cody↗
DOE OSTI2022

Correlated nanoelectronics and the second quantum revolution

The growing field of correlated nanoelectronics exists at the intersection of two established fields: correlated oxide electronics and semiconductor nanoelectronics. The development of quantum technologies that exploit quantum coherence and entanglement for the purposes of computation, simulation, and sensing will require complex material properties to be controlled at nanoscale dimensions. Heterostructures and nanostructures formed at the interface between LaAlO 3 and SrTiO 3 exhibit striking behavior that arises from the ability to program the conductive behavior at extreme nanoscale dimensions. The active electronic layer, SrTiO 3 , exhibits a wide range of gate-tunable phenomena such as ferroelectricity, ferroelasticity, magnetism, superconductivity, and spin–orbit coupling, all of which can be controlled at the nanoscale using two reversible methods: conductive atomic force microscope lithography and ultra-low-voltage electron beam lithography. Mesoscopic devices such as single-electron transistors and quasi-one-dimensional electron waveguides can be “sketched” using these techniques, and the properties of these devices differ significantly from those created from traditional semiconductors, such as Si or GaAs. The strongly correlated nature of the SrTiO 3 system is evident from superconducting behavior as well as a state in which electrons are paired outside the superconducting state. A highly exotic phase was discovered in which a degenerate quantum liquid is formed from bound states of n = 2, 3, 4, … electrons. Further development of correlated nanoelectronics based on the LaAlO 3 /SrTiO 3 system can potentially lead to a general platform for quantum simulation as well as a pathway for the development of highly entangled states of multiple photons.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Nonvolatile Memristive Effect in Few-Layer CrI 3 Driven by Electrostatic Gating

The potential of memristive devices for applications in nonvolatile memory and neuromorphic computing has sparked considerable interest, particularly in exploring memristive effects in two-dimensional (2D) magnetic materials. However, the progress in developing nonvolatile, magnetic field-free memristive devices using 2D magnets has been limited. In this work, we report an electrostatic-gating-induced nonvolatile memristive effect in CrI 3 -based tunnel junctions. The few-layer CrI 3 -based tunnel junction manifests notable hysteresis in its tunneling resistance as a function of gate voltage. We further engineered a nonvolatile memristor using the CrI 3 tunneling junction with low writing power and at zero magnetic field. We show that the hysteretic transport observed is not a result of trivial effects or inherent magnetic properties of CrI 3 . We propose a potential association between the memristive effect and the newly predicted ferroelectricity in CrI 3 via gating-induced Jahn–Teller distortion. Furthermore, our work illuminates the potential of 2D magnets in developing next-generation advanced computing technologies.

2D magnet↗