FPGA Computing
The articles in this special section focus on cutting-edge research on topics that relate to field programmable gate arrays (FPGA) in computing.
97 MATHEMATICS AND COMPUTING↗
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An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction
This paper presented a non-uniform multiphase (NUMP) time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) with real-time automatic temperature compensation. NUMP-TDC is a novel, low-cost, high-performance TDC that has achieved an excellent performance in Altera Cyclone V FPGA. The root mean square (RMS) for the intrinsic timing resolution was 2.3 ps. However, the propagation delays in the delay chain of some FPGAs (for example, the Altera Cyclone 10 LP) vary significantly as the temperature changes. Thus, the timing performances of NUMP-TDCs implemented in those FPGAs are significantly impacted by temperature fluctuations. In this study, a simple method was developed to monitor variations in propagation delays using two registers deployed at both ends of the delay chain and compensate for changes in propagation delay using a look-up table (LUT). When the variations exceeded a certain threshold, the LUT for the delay correction was updated, and a bin-by-bin correction was launched. Using this correction approach, a resolution of 8.8 ps RMS over a wide temperature range (5 °C to 80 °C) had been achieved in a NUMP-TDC implemented in a Cyclone 10 LP FPGA.
59 BASIC BIOLOGICAL SCIENCES↗
ESnet/JLab FPGA Accelerated Transport
To increase the science rate for high data rates/volumes, Thomas Jefferson National Accelerator Facility (JLab) has partnered with Energy Sciences Network (ESnet) to define an edge to data center traffic shaping / steering transport capability featuring data event aware network shaping and forwarding. The keystone of this ESnet+JLab FPGA Accelerated Transport (EJFAT) is the joint development of an AI/ML directed dynamic compute work Load Balancer (LB) of UDP streamed data. The LB is a suite consisting of a Field Programmable Gate Array (FPGA) executing the dynamically configurable, low fixed latency LB data plane featuring real-time packet redirection and high throughput, and a control plane running on the FPGA host computer that monitors network and compute farm telemetry in order to make dynamic AI/ML guided decisions for destination compute host redirection/load balancing and destination resource provisioning. The LB provides for three-tier horizontal scaling across LB suites, core compute hosts, and CPUs within a host. The LB effectively provides seamless integration of edge/core computing to support direct experimental data processing for immediate use by JLab science programs and others such as the EIC as well as data centers of the future requiring high throughput and low latency for both hot and cooled data for both running experiment data acquisition systems and data center use cases.
97 MATHEMATICS AND COMPUTING↗
Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines
Field programmable gate array (FPGA) is widely used in the acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the trade-off between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. Here, we propose a ferroelectric field-effect transistor (FeFET)–based context-switching FPGA supporting dynamic reconfiguration to break this trade-off, enabling loading of arbitrary configuration without interrupting the active configuration execution. Leveraging the intrinsic structure and nonvolatility of FeFETs, compact FPGA primitives are proposed and experimentally verified. The evaluation results show our design shows a 63.0%/74.7% reduction in a look-up table (LUT)/connection block (CB) area and 82.7%/53.6% reduction in CB/switch box power consumption with a minimal penalty in the critical path delay (9.6%). Besides, our design yields significant time savings by 78.7 and 20.3% on average for context-switching and dynamic reconfiguration applications, respectively.
97 MATHEMATICS AND COMPUTING↗
High performance context switching for virtualized FPGA accelerators
A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.
42 ENGINEERING↗
Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator
A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.
42 ENGINEERING↗
Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator
A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.
Asaad, Sameh W.↗
Architecture Of A Multi-channel Data Streaming Device With An Fpga As A Coprocessor
The design of a data acquisition system often involves the integration of a Field Programmable Gate Array (FPGA) with analog front-end components to achieve precise timing and control. Reuse of these hardware systems can be difficult since they need to be tightly coupled to the communications interface and timing requirements of the specific ADC used. A hybrid design exploring the use of FPGA as a coprocessor to a traditional CPU in a dataflow architecture is presented. Reduction in the volume of data and gradual transitioning of data processing away from a hard real-time environment are both discussed. Chief design concerns, including data throughput and precise synchronization with external stimuli, are addressed. The discussion is illustrated by the implementation of a multi-channel digital integrator, a device based entirely on commercial off-the-shelf (COTS) equipment.
Nogiec, Jerzy M.↗
The JET upgraded toroidal Alfvén Eigenmode Diagnostic System
The Alfvén Eigenmode Active Diagnostic system (AEAD) has undergone a major upgrade and redesign to provide a state-of-the-art excitation and real-time detection system for JET. The new system consists of individual 4 kW amplifiers allowing for increased current, separate excitation and real time control of relative phasing between antenna currents. The amplifiers have a frequency range of 10–1000 kHz, divided into various frequency bands by external matching filters. Due to the varying transmission line impedance throughout the frequency range, the amplifiers were designed with a very high resilience to reflected power. The existing amplifier control electronics have been replaced with a digital control system incorporating a National Instruments platform and Field Programmable Gate Array (FPGA) modules for frequency, gain and phase control with a frequency and phase resolution of less than 1 kHz and 1 degree respectively. Complementing the digital control system is the Protection and Control System, which utilizes Field Programmable Analog Arrays (FPAAs) and an array of electronic devices to monitor and control the AEAD. New capabilities such as independent antenna current/phase control, allow for improved excitation control, better definition of antenna spectrum combined with enhanced system reliability. This paper will review the new AEAD system, its unique capabilities and improvements over the previous diagnostic system.
70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark
We present our development experience and recent results for the MLPerf Tiny Inference Benchmark on field-programmable gate array (FPGA) platforms. We use the open-source hls4ml and FINN workflows, which aim to democratize AI-hardware codesign of optimized neural networks on FPGAs. We present the design and implementation process for the keyword spotting, anomaly detection, and image classification benchmark tasks. The resulting hardware implementations are quantized, configurable, spatial dataflow architectures tailored for speed and efficiency and introduce new generic optimizations and common workflows developed as a part of this work. The full workflow is presented from quantization-aware training to FPGA implementation. The solutions are deployed on system-on-chip (Pynq-Z2) and pure FPGA (Arty A7-100T) platforms. The resulting submissions achieve latencies as low as 20 $\mu$s and energy consumption as low as 30 $\mu$J per inference. We demonstrate how emerging ML benchmarks on heterogeneous hardware platforms can catalyze collaboration and the development of new techniques and more accessible tools.
Borras, Hendrik↗
Nanosecond machine learning regression with deep boosted decision trees in FPGA for high energy physics
We present a novel application of the machine learning / artificial intelligence method called boosted decision trees to estimate physical quantities on field programmable gate arrays (FPGA). The software package fwXmachina features a new architecture called parallel decision paths that allows for deep decision trees with arbitrary number of input variables. It also features a new optimization scheme to use different numbers of bits for each input variable, which produces optimal physics results and ultraefficient FPGA resource utilization. Problems in high energy physics of proton collisions at the Large Hadron Collider (LHC) are considered. Estimation of missing transverse momentum (E T miss ) at the first level trigger system at the High Luminosity LHC (HL-LHC) experiments, with a simplified detector modeled by Delphes, is used to benchmark and characterize the firmware performance. The firmware implementation with a maximum depth of up to 10 using eight input variables of 16-bit precision gives a latency value of $\mathcal{O}$(10) ns, independent of the clock speed, and $\mathcal{O}$(0.1)% of the available FPGA resources without using digital signal processors.
Instruments & Instrumentation↗
Lax-Oleinik-Type Formulas and Efficient Algorithms for Certain High-Dimensional Optimal Control Problems
Two of the main challenges in optimal control are solving problems with state-dependent running costs and developing efficient numerical solvers that are computationally tractable in high dimension. In this paper, we provide analytical solutions to certain optimal control problems whose running cost depends on the state variable and with constraints on the control. We also provide Lax-Oleinik-type representation formulas for the corresponding Hamilton-Jacobi partial differential equations with state-dependent Hamiltonians. Additionally, we present an efficient, grid-free numerical solver based on our representation formulas, which is shown to scale linearly with the state dimension, and thus, to overcome the curse of dimensionality. Using existing optimization methods and the min-plus technique, we extend our numerical solvers to address more general classes of convex and nonconvex initial costs. We demonstrate the capabilities of our numerical solvers using implementations on a central processing unit (CPU) and a field-programmable gate array (FPGA). In several cases, our FPGA implementation obtains over a 10 times speedup compared to the CPU, which demonstrates the promising performance boosts FPGAs can achieve. Furthermore, our numerical results show that our solvers have the potential to serve as a building block for solving broader classes of high-dimensional optimal control problems in real-time.
97 MATHEMATICS AND COMPUTING↗
Virtual FPGA management and optimization system
A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.
97 MATHEMATICS AND COMPUTING↗
Control system backplane monitoring with FPGA
Described herein are various technologies for monitoring the backplane of a control system and detecting modifications of the control system (e.g., removal of modules, firmware updates, etc.). A monitoring device includes a field programmable gate array (FPGA), and is connected to the backplane of the control system. The monitoring device receives signals, by way of the backplane, that are communicated among modules connected to the backplane. The monitoring device detects a modification to the control system based upon the received signals.
97 MATHEMATICS AND COMPUTING↗
First application of a digital mirror Langmuir probe for real-time plasma diagnosis
For the first time, a digital Mirror Langmuir probe (MLP) has successfully sampled plasma temperature, ion saturation current, and floating potential together on a single probe tip in real time in a radio-frequency driven helicon linear plasma device. This is accomplished by feedback control of the bias sweep to ensure a good fit to I-V characteristics with a high frequency, high power digital amplifier and field-programmable gate array (FPGA) controller. Measurements taken by the MLP were validated by a low speed I-V characteristic manually collected during static plasma conditions. Plasma fluctuations, induced by varying the axial magnetic field (f̃ = 10 Hz), were also successfully monitored with the MLP. Further refinement of the digital MLP pushes it towards a turn-key system that minimizes the time to deployment and lessens the learning curve, positioning the digital MLP as a capable diagnostic for the study of low radio-frequency plasma physics. These demonstrations bolster confidence in fielding such digital MLP diagnostics in magnetic confinement experiments with high spatial and adequate temporal resolution such as edge plasma, scrape-off layer, and divertor probes.
70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
Lightweight Embedded Controller in Advanced FPGA SoC for Radar Signal Processing [Poster]
The objective of the project is to demonstrate that critical control functions can be implemented using little resources in modern microelectronics. A finite state machine (Figure 1) is implemented onto a field programmable gate array (FPGA). The functionality of the system is demonstrated by sending binary instructions to the controller. The controller transmits patterns through an LED, controls an electromechanical device, and uses pulse-width modulation (PWM) for radar functions.
42 ENGINEERING↗
E-1039 "SpinQuest" FPGA Trigger
The SpinQuest experiment will measure an azimuthal asymmetry in the Drell-Yan production of $\mu+$ $\mu-$ pairs from 120 GeV/c proton interactions with polarized nucleons to extract the Sivers function for $\bar{u}$ and $\bar{d}$. A large combinatorial background from muons produced in the beam dump requires a trigger which is capable of identifying dimuon pairs originating from the target in a high rate environment. The trigger system consists of four stations of scintillator hodoscopes whose 96 channels are digitized and processed by field-programmable gate array (FPGA) based VMEbus modules. Hodoscope hit patterns are compared to predetermined sets, chosen from Monte Carlo simulations, in a tiered lookup table to generate trigger decisions. The design and current status of the FPGA trigger will be presented and planned upgrades to the trigger logic will be discussed.
72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions
Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.
97 MATHEMATICS AND COMPUTING↗