Radiation Effects on Advanced Flash Memories
Flash memories have evolved very rapidly in recent years.
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Radiation Effects on Advanced Flash Memories
Flash memories have evolved very rapidly in recent ears. New design techniques such as multilevel storage have been proposed to increase storage density, and are now available commercially. Threshold voltage distributions for single- and three-level technologies are compared. In order to implement this technology special circuitry must be added to allow the amount of charge stored in the floating gate to be controlled within narrow limits during the writing and also to detect the different amounts of charge during reading.
Nguyen, D. N.↗
Evaluation of Radiation Effects in Flash Memories
Features of flash memories: Flash memories are non-volatile; that is they do not require power to retain the information in its memory. They can be erased and written to while the device is still in the circuit.
Radiation effects↗
Non Volatile Flash Memory Radiation Tests
Commercial flash memory industry has experienced a fast growth in the recent years, because of their wide spread usage in cell phones, mp3 players and digital cameras. On the other hand, there has been increased interest in the use of high density commercial nonvolatile flash memories in space because of ever increasing data requirements and strict power requirements. Because of flash memories complex structure; they cannot be treated as just simple memories in regards to testing and analysis. It becomes quite challenging to determine how they will respond in radiation environments.
single event upset results↗
Hold-up power supply for flash memory
A hold-up power supply for flash memory systems is provided. The hold-up power supply provides the flash memory with the power needed to temporarily operate when a power loss exists. This allows the flash memory system to complete any erasures and writes, and thus allows it to shut down gracefully. The hold-up power supply detects when a power loss on a power supply bus is occurring and supplies the power needed for the flash memory system to temporally operate. The hold-up power supply stores power in at least one capacitor. During normal operation, power from a high voltage supply bus is used to charge the storage capacitors. When a power supply loss is detected, the power supply bus is disconnected from the flash memory system. A hold-up controller controls the power flow from the storage capacitors to the flash memory system. The hold-up controller uses feedback to assure that the proper voltage is provided from the storage capacitors to the flash memory system. This power supplied by the storage capacitors allows the flash memory system to complete any erasures and writes, and thus allows the flash memory system to shut down gracefully.
Ott, William E.↗
Flash memory management system and method utilizing multiple block list windows
The present invention provides a flash memory management system and method with increased performance. The flash memory management system provides the ability to efficiently manage and allocate flash memory use in a way that improves reliability and longevity, while maintaining good performance levels. The flash memory management system includes a free block mechanism, a disk maintenance mechanism, and a bad block detection mechanism. The free block mechanism provides efficient sorting of free blocks to facilitate selecting low use blocks for writing. The disk maintenance mechanism provides for the ability to efficiently clean flash memory blocks during processor idle times. The bad block detection mechanism provides the ability to better detect when a block of flash memory is likely to go bad. The flash status mechanism stores information in fast access memory that describes the content and status of the data in the flash disk. The new bank detection mechanism provides the ability to automatically detect when new banks of flash memory are added to the system. Together, these mechanisms provide a flash memory management system that can improve the operational efficiency of systems that utilize flash memory.
Chow, James↗
Some Improvements in Utilization of Flash Memory Devices
Two developments improve the utilization of flash memory devices in the face of the following limitations: (1) a flash write element (page) differs in size from a flash erase element (block), (2) a block must be erased before its is rewritten, (3) lifetime of a flash memory is typically limited to about 1,000,000 erases, (4) as many as 2 percent of the blocks of a given device may fail before the expected end of its life, and (5) to ensure reliability of reading and writing, power must not be interrupted during minimum specified reading and writing times. The first development comprises interrelated software components that regulate reading, writing, and erasure operations to minimize migration of data and unevenness in wear; perform erasures during idle times; quickly make erased blocks available for writing; detect and report failed blocks; maintain the overall state of a flash memory to satisfy real-time performance requirements; and detect and initialize a new flash memory device. The second development is a combination of hardware and software that senses the failure of a main power supply and draws power from a capacitive storage circuit designed to hold enough energy to sustain operation until reading or writing is completed.
Gender, Thomas K.↗
Radiation Tests of Highly scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories--Update 2011
High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) 32Gb and multi-level cell (MLC) 64Gb NAND flash memories manufactured by Micron Technology.
Heavy ion↗
Flash memory reliability NEPP 2008 task final report
This is the preliminary report which is based on the flash memory reliability studies conducted during the first year (2008) of the multi-year NEPP task. The report outlines the technology and reliability challenges for advanced flash memory technologies, summarizes the test results and analyses of reliability characterizations performed on the selected flash memory devices during 2008, and provides the preliminary thoughts on the risk mitigation approaches on using advanced flash memory technologies for space applications.
Chen, Yuan↗
Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2010
High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) and multi-level cell (MLC) NAND flash memories manufactured by Micron Technology.
Irom, Farokh↗
NOR Flash Memory Scrubbing Application for Boot File Preservation of NASA’s Descent and Landing Computer (DLC)
Progress on NASA’s Safe and Precise Landing Integrated Capabilities Evolution (SPLICE) project continues, specifically with this development of the Descent and Landing Computer (DLC). One of the DLC’s primary contributions as a SPLICE technology is its implementation of algorithms and operation of sensors to autonomously guide a spacecraft in performing more precise and safer landings on celestial bodies such as the Moon and Mars [1]. The second iteration of the DLC is known as the Engineering Test Unit (ETU) and one of its desired functionalities is the ability to preserve the fidelity of the system’s boot file through the use of memory scrubbing [2]. The ETU has two primary boards, one for housing a Multi-Processor System on a Chip (MPSoC) and the other for housing a Xilinx Kintex Ultrascale FPGA*. To emulate a memory scrubbing function implemented on the ETU’s FPGA board, the design and testing of a software application was performed on a Xilinx KCU105 FPGA evaluation board. The memory scrubbing application had to meet certain key criteria such as (1) properly utilize with the flash memory’s Serial Peripheral Interface (SPI) to read, write, and erase flash memory properly, (2) be able to detect arbitrarily large or small amounts of bit-errors, (3) be able to correct all detected errors, and (4) perform memory scrubbing indefinitely and autonomously. A prototype implementation was constructed and tested, demonstrating successful detection and correction of bit errors in multiple configurations. In the form of burst errors or singular bit flips, and in amounts of errors ranging from one to fifteen (per 256 Bytes), the application was successful in preserving memory fidelity.
Flash memory↗
Micron MT29F1T08CMHBBJ4 1Tb NAND Flash Memory Single Event Effect Characterization Test Report
The purpose of this testing is to characterize the Single-Event Effect (SEE) response of the Micron MT29F1T08CMHBBJ4 3D NAND Flash memory. The MT29F1T08CMHBBJ4 is a 1Tb NAND Flash memory, consisting of a four-die stack of 256Gb MLC dice packaged in a 132-ball VBGA package. All data presented is the result of testing only the top die (256Gb) of the package. Testing was performed at two heavy-ion cyclotron facilities with an identical test setup, over the course of four test trips from 2017-2019.
Single Event Effect (SEE)↗
Implementation of Self-Align Local Poly Interconnection on 0.25 Micron Flash Memory
For ETOX Flash technology. the self-aligned source module plays a critical role in minimizing cell size. For advanced Flash technology using the shallow-trench isolation (STI) scheme, however, it is difficult to form a stable source line. The Flash process in this experiment features an ETOX structure and with SIN spacer. Poly-Si (implanted poly) is used as the local interconnection material connecting the source line and was successfully implemented in the ETOX flash array in this paper.
C H Lee↗
Space radiation effects in advanced flash memories
This paper discusses the space radiation effects in advanced flash memories.
space↗
Space Radiation Effects in Advanced Flash Memories
Memory storage requirements in space systems have steadily increased, much like storage requirements in terrestrial systems. Large arrays of dynamic memories (DRAMs) have been used in solid-state recorders, relying on a combination of shielding and error-detection-and correction (EDAC) to overcome the extreme sensitivity of DRAMs to space radiation. For example, a 2-Gbit memory (with 4-Mb DRAMs) used on the Clementine mission functioned perfectly during its moon mapping mission, in spite of an average of 71 memory bit flips per day from heavy ions. Although EDAC worked well with older types of memory circuits, newer DRAMs use extremely complex internal architectures which has made it increasingly difficult to implement EDAC. Some newer DRAMs have also exhibited catastrophic latchup. Flash memories are an intriguing alternative to DRAMs because of their nonvolatile storage and extremely high storage density, particularly for applications where writing is done relatively infrequently. This paper discusses radiation effects in advanced flash memories, including general observations on scaling and architecture as well as the specific experience obtained at the Jet Propulsion Laboratory in evaluating high-density flash memories for use on the NASA mission to Europa, one of Jupiter's moons. This particular mission must pass through the Jovian radiation belts, which imposes a very demanding radiation requirement.
Johnston, A. H.↗
Radiation tests of highly scaled high density commercial nonvolatile NAND flash memories update 2009
Heavy ion single-event measurements on a variety of high density commercial NAND flash memories are reported. Three single event effect (SEE) phenomena are examined: single effect upsets (SEUs), single event functional interrupts (SEFIs), and catastrophic loss of ability to erase and program the device. Also, radiation results of multilevel flash technology are compared with results from single-level flash technology. These commercial high density memories appear to be much less susceptible to SEE and have better TID response compared to older generations of flash memories. The single-level devices are less sensitive to SEUs than multi-level devices. The charge pump in this study survived up to 600 krads. A new high current phenomenon in high density NAND flash memories is also discussed.
Nguyen, Duc N.↗
Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2012
The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.
Irom, Farokh↗
Radiation tests of highly scaled, high-density, commercial, nonvolatile NAND flash memories— update 2012
The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.
Allen, Gregory R.↗