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Prediction of Alpha-Particle-Immune Gate-All-Around Field-Effect Transistors (GAA-FET) Based SRAM Design

Alpha particles are known to be a major source of particles creating soft errors in semiconductor devices, such as content flipping in Static Random-Access Memory (SRAM). Recent advancements in transistor nodes have led to the introduction of Gate-All-Around Field Effect Transistors (GAA-FETs), which have better gate control, thus better electrostatics. Moreover, the introduction of bottom dielectric isolation (BDI) eliminates substrate leakage and thus is expected to enhance its radiation hardness. It is thus important to explore if one can design an SRAM that is completely radiation-hard to alpha particles. In this paper, using 3D Technology Computer-Aided-Design (TCAD) simulations, we show that it is possible to design an SRAM using GAA-FET technology so that it is immune to single alpha particle radiation error. In other words, with the design, there will be no single-event upset (SEU) due to alpha particles. We first use ab initio calculations in PHITS to show that there is a maximum linear energy transfer (LET), LET max , for the alpha particle in Si and Si x Ge 1-x . Based on that, by de signing a sub-7nm GAA-FET-based SRAM with BDI, we show that the SRAM does not flip even if the particle strike is in the worst-case scenario for LET > LET max .

42 ENGINEERING↗

Gate-All-Around Nanowire Field-Effect Transistors: A Historical Perspective

The development of transistor architectures, evolving from 2D planar metal-oxide-semiconductor field-effect transistors (MOSFETs) to FinFETs and then to gate-all-around nanowire (GAANW) FETs, plays a crucial role in downscaling technology nodes in the semiconductor industry. This perspective reviews the concept of MOSFETs and summarizes this historical development with particular emphasis on GAANW transistors due to their importance in next-generation technology for nodes below 3 nm. Specifically, the concept of GAANW transistors and their advantages over planar and FinFET devices for further scaling are presented, along with a discussion of their transition from early conceptual ideas to laboratory demonstrations and, ultimately, industrial adoption. Furthermore, potential solutions, such as complementary FETs (CFETs) and 2D semiconductor-based FETs, and their associated challenges for the future generation, known as the Angstrom Era, are discussed in a technological roadmap. In conclusion, this perspective may inspire both industry and academia in future research directions for realizing the Angstrom Era.

gate-all-around transistors↗

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Transistor↗

Probability Density Function for the spatial and intensity distribution of neutron-induced defects in Silicon

The ability to model semiconductor device degradation under neutron irradiation depends upon having a robust modeling capability for the neutron-induced collision cascades as well as a means to analytically fit the resulting probability distributions of defect production and ionizing energy deposition for purposes of extrapolation to low-probability, high-consequence scenarios. In this paper, the widely-utilized binary collision approximation codes MARLOWE and SRIM are deployed in conjunction with a critical examination of their parameterizations as benchmarked against higher-fidelity molecular dynamics simulations. A simple 3-parameter form described by the Generalized Logistic Distribution is shown to be a good fit to Frenkel pair and ionization intensity distributions in bulk silicon. The BCA codes are then applied to simulate cascades in 5 nm layers of a representative gate-all-around nanosheet transistor, where joint probability distributions of threshold levels of damage to multiple layers are evaluated.

36 MATERIALS SCIENCE↗

One Time Programmable Antifuse Memory Based on Bulk Junctionless Transistor

One time programmable (OTP) antifuse base memory is demonstrated based on a bulk junctionless gate-all-around (GAA) nanowire transistor technology. The presented memory consists of a single transistor (1T) footprint without any process modification. The source/drain (S/D) and gate respectively become bit line and word line where the antifuse is formed by oxide breakdown across the gate and the channel. The channel is connected directly to the bit line due to junctionless S/D and inherently isolated from the neighboring cell by the GAA channel. Therefore, an array of 1T antifuse OTP can be a candidate for the sub-5-nanometer technology node.

Antifuse↗

Statistical analysis of displacement damage in small devices from neutron and ion irradiation

Modern semiconductor devices, such as gate-all-around nanosheet field-effect transistors (GAA NS FETs), are smaller than displacement damage cascades from fission neutrons. In this regime, device failure may occur through low-probability single events, rather than by parametric degradation previously seen in larger devices. Here, we present a statistical model that predicts the probability of a damage event in a small device and the probability distribution of the magnitude, i.e., number of displacements within the device, from each event. The model is developed first for neutron irradiation and then for energetic ion irradiation. The model is consistent with results from recent experiments in which lithium-ion irradiation produced stepwise increases in subthreshold current in GAA NS FETs.

Wampler, W. R.↗