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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records

Generating multi-scale Li-ion battery cathode particles with radial grain architectures using stereological generative adversarial networks

Abstract Understanding structure-property relationships of Li-ion battery cathodes is crucial for optimizing rate-performance and cycle-life resilience. However, correlating the morphology of cathode particles, such as in LiNi0.8Mn0.1Co0.1O2 (NMC811), and their inner grain architecture with electrode performance is challenging, particularly, due to the significant length-scale difference between grain and particle sizes. Experimentally, it is not feasible to image such a high number of particles with full granular detail. A second challenge is that sufficiently high-resolution 3D imaging techniques remain expensive and are sparsely available at research institutions. Here, we present a stereological generative adversarial network-based model fitting approach to tackle this, that generates representative 3D information from 2D data, enabling characterization of materials in 3D using cost-effective 2D data. Once calibrated, this multi-scale model can rapidly generate virtual cathode particles that are statistically similar to experimental data, and thus is suitable for virtual characterization and materials testing through numerical simulations. A large dataset of simulated particles with inner grain architecture has been made publicly available.

25 ENERGY STORAGE↗

Massively Parallel Solution of Poisson Equation on Coarse Grain MIMD Architectures

In this paper a new algorithm, designated as Fast Invariant Imbedding algorithm, for solution of Poisson equation on vector and massively parallel MIMD architectures is presented. This algorithm achieves the same optimal computational efficiency as other Fast Poisson solvers while offering a much better structure for vector and parallel implementation. Our implementation on the Intel Delta and Paragon shows that a speedup of over two orders of magnitude can be achieved even for moderate size problems.

parallel algorithms MIMD parallel architectures↗

Linear complexity

We present factorization and solution phases for a new linear complexity direct solver designed for concurrent batch operations on fine-grained parallel architectures, for matrices amenable to hierarchical representation. We focus on the strong-admissibility-based $\mathscr{H}^{2}$ format, where strong recursive skeletonization factorization compresses remote interactions. We build upon previous implementations of $\mathscr{H}^{2}$ matrix construction for efficient factorization and solution algorithm design, which are illustrated graphically in stepwise detail. The algorithms are ‘blackbox’ in the sense that the only inputs are the matrix and right-hand side, without analytical or geometrical information about the origin of the system. We demonstrate linear complexity scaling in both time and memory on four representative families of dense matrices up to one million in size. Parallel scaling up to 16 threads is enabled by a multi-level matrix graph coloring and avoidance of dynamic memory allocations thanks to prefix-sum memory management. An experimental backward error analysis is included. We break down the timings of different phases, identify phases that are memory-bandwidth limited, and discuss alternatives for phases that may be sensitive to the trend to employ lower precisions for performance.

Boukaram, Wajih↗

Unconventional compute methods and future challenges for superconducting digital computing

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

EDA tools↗

Evolution of connectivity architecture in the Drosophila mushroom body

Brain evolution has primarily been studied at the macroscopic level by comparing the relative size of homologous brain centers between species. How neuronal circuits change at the cellular level over evolutionary time remains largely unanswered. Here, using a phylogenetically informed framework, we compare the olfactory circuits of three closely related Drosophila species that differ in their chemical ecology: the generalists Drosophila melanogaster and Drosophila simulans and Drosophila sechellia that specializes on ripe noni fruit. We examine a central part of the olfactory circuit that, to our knowledge, has not been investigated in these species—the connections between projection neurons and the Kenyon cells of the mushroom body—and identify species-specific connectivity patterns. We found that neurons encoding food odors connect more frequently with Kenyon cells, giving rise to species-specific biases in connectivity. These species-specific connectivity differences reflect two distinct neuronal phenotypes: in the number of projection neurons or in the number of presynaptic boutons formed by individual projection neurons. Finally, behavioral analyses suggest that such increased connectivity enhances learning performance in an associative task. Our study shows how fine-grained aspects of connectivity architecture in an associative brain center can change during evolution to reflect the chemical ecology of a species.

59 BASIC BIOLOGICAL SCIENCES↗

Strategies for concurrent processing of complex algorithms in data driven architectures

The performance modeling and enhancement for periodic execution of large-grain, decision-free algorithms in data flow architectures is examined. Applications include real-time implementation of control and signal processing algorithms where performance is required to be highly predictable. The mapping of algorithms onto the specified class of data flow architectures is realized by a marked graph model called ATAMM (Algorithm To Architecture Mapping Model). Performance measures and bounds are established. Algorithm transformation techniques are identified for performance enhancement and reduction of resource (computing element) requirements. A systematic design procedure is described for generating operating conditions for predictable performance both with and without resource constraints. An ATAMM simulator is used to test and validate the performance prediction by the design procedure. Experiments on a three resource testbed provide verification of the ATAMM model and the design procedure.

Stoughton, John W.↗

Strategies for concurrent processing of complex algorithms in data driven architectures

Performance modeling and performance enhancement for periodic execution of large-grain, decision-free algorithms in data flow architectures are discussed. Applications include real-time implementation of control and signal processing algorithms where performance is required to be highly predictable. The mapping of algorithms onto the specified class of data flow architectures is realized by a marked graph model called algorithm to architecture mapping model (ATAMM). Performance measures and bounds are established. Algorithm transformation techniques are identified for performance enhancement and reduction of resource (computing element) requirements. A systematic design procedure is described for generating operating conditions for predictable performance both with and without resource constraints. An ATAMM simulator is used to test and validate the performance prediction by the design procedure. Experiments on a three resource testbed provide verification of the ATAMM model and the design procedure.

Som, Sukhamoy↗

Algorithm To Architecture Mapping Model (ATAMM) multicomputer operating system functional specification

A functional description of the ATAMM Multicomputer Operating System is presented. ATAMM (Algorithm to Architecture Mapping Model) is a marked graph model which describes the implementation of large grained, decomposed algorithms on data flow architectures. AMOS, the ATAMM Multicomputer Operating System, is an operating system which implements the ATAMM rules. A first generation version of AMOS which was developed for the Advanced Development Module (ADM) is described. A second generation version of AMOS being developed for the Generic VHSIC Spaceborne Computer (GVSC) is also presented.

Mielke, R.↗

Achieving strength-ductility synergy in hierarchical aluminum metal matrix composites via friction extrusion

We report the fabrication of aluminum metal matrix composites (Al-MMCs) with hierarchical architectures via friction extrusion (FE), a scalable, single-step, solid-phase processing technique. Precursor pucks containing 0–15 vol% Al₂O₃ particles were extruded into fully dense AA6061-based composite rods. The FE induced a tree-ring-like architecture of concentric particle-rich and particle-lean bands, yielding refined grains in particle-rich regions and coarser grains elsewhere. At the nanoscale, magnesium in AA6061 selectively reacted with Al₂O₃ particles to form virus-like nodes, improving particle–matrix bonding. This multi-scale design strategy, combining mesoscale architecture, microscale grain refinement, and nanoscale interface engineering overcome the conventional strength–ductility trade-off. Tensile testing showed substantial increases in yield and ultimate tensile strengths while retaining high ductility ( > 20%). Enhanced strain hardening, driven by the accumulation of geometrically necessary dislocations at interfaces, contributed to the performance. The hierarchical microstructure produced by FE demonstrates a promising pathway for scalable fabrication of lightweight MMCs for structural applications requiring a combined high strength and ductility.

Kalsar, Rajib [Pacific Northwest National Laborato↗

Spectral element methods: Algorithms and architectures

Spectral element methods are high-order weighted residual techniques for partial differential equations that combine the geometric flexibility of finite element methods with the rapid convergence of spectral techniques. Spectral element methods are described for the simulation of incompressible fluid flows, with special emphasis on implementation of spectral element techniques on medium-grained parallel processors. Two parallel architectures are considered: the first, a commercially available message-passing hypercube system; the second, a developmental reconfigurable architecture based on Geometry-Defining Processors. High parallel efficiency is obtained in hypercube spectral element computations, indicating that load balancing and communication issues can be successfully addressed by a high-order technique/medium-grained processor algorithm-architecture coupling.

Fischer, Paul↗

Spectral element methods - Algorithms and architectures

Spectral element methods are high-order weighted residual techniques for partial differential equations that combine the geometric flexibility of finite element methods with the rapid convergence of spectral techniques. Spectral element methods are described for the simulation of incompressible fluid flows, with special emphasis on implementation of spectral element techniques on medium-grained parallel processors. Two parallel architectures are considered; the first, a commercially available message-passing hypercube system; the second, a developmental reconfigurable architecture based on Geometry-Defining Processors. High parallel efficiency is obtained in hypercube spectral element computations, indicating that load balancing and communication issues can be successfully addressed by a high-order technique/medium-grained processor algorithm-architecture coupling.

Fischer, Paul↗

Simulator for concurrent processing data flow architectures

A software simulator capability of simulating execution of an algorithm graph on a given system under the Algorithm to Architecture Mapping Model (ATAMM) rules is presented. ATAMM is capable of modeling the execution of large-grained algorithms on distributed data flow architectures. Investigating the behavior and determining the performance of an ATAMM based system requires the aid of software tools. The ATAMM Simulator presented is capable of determining the performance of a system without having to build a hardware prototype. Case studies are performed on four algorithms to demonstrate the capabilities of the ATAMM Simulator. Simulated results are shown to be comparable to the experimental results of the Advanced Development Model System.

Malekpour, Mahyar R.↗

ATAMM analysis tool

Diagnostics software for analyzing Algorithm to Architecture Mapping Model (ATAMM) based concurrent processing systems is presented. ATAMM is capable of modeling the execution of large grain algorithms on distributed data flow architectures. The tool graphically displays algorithm activities and processor activities for evaluation of the behavior and performance of an ATAMM based system. The tool's measurement capabilities indicate computing speed, throughput, concurrency, resource utilization, and overhead. Evaluations are performed on a simulated system using the software tool. The tool is used to estimate theoretical lower bound performance. Analysis results are shown to be comparable to the predictions.

Jones, Robert↗

Topology-Informed Design Rules for Deconstructable Thermoset Copolymer Networks

Existing models of thermoset deconstruction facilitated by incorporating cleavable comonomers rely on a mean-field reverse gel point paradigm, which predicts network dissolution once cleavable bonds reach a critical stoichiometric threshold, but does not account for where those bonds reside within the network architecture. Using reactive coarse-grained molecular dynamics simulations coupled with graph-theoretic analysis, we extend this stoichiometric picture to show that deconstructability is governed by the curing-imprinted network topology rather than stoichiometry alone. This topological organization is hierarchical: at the local scale, the elastic effectiveness of cross-link junctions determines which cross-links constitute the load-bearing scaffold; at the mesoscale, the cross-linking rate kinetically templates that scaffold into topologically modular communities─densely cross-linked clusters connected by sparse bridging strands that sustain network connectivity. Using betweenness centrality to identify nodes that disproportionately lie on intercommunity shortest paths, we demonstrate that effective deconstruction of the network into macromolecular fragments requires cleavable comonomers to intercept these high-centrality bridging strands. We further find that under uniform, disassortative comonomer incorporation, this topological requirement provides a mechanistic basis for extending the reverse gel point to incorporate network topology. We also show that modularity imposes a fundamental limit on fragment uniformity that persists even when the centrality requirement is met. Finally, we demonstrate that chain stiffness provides a nearly independent lever to suppress mechanically redundant cross-links and raise the glass transition temperature without significantly altering the deconstruction outcome. Together, these findings reframe the thermoset design space around network topology and provide actionable guidelines for engineering thermoset copolymers with predictable deconstructability and targeted thermomechanical performance.

coarse-grained molecular dynamics↗

New Deformation Mechanisms in Nanocrystalline Nano-porous Small Scale Metals as Defined by Kinetically-driven Microstructures

This report describes recent advances in the design and fabrication of nanostructured metallic pillars with hierarchical microstructures using a novel nanoscale additive manufacturing approach. Through a hydrogel-infusion-based two-photon lithography (TPL) method, we successfully fabricated 3D nickel nanopillars exhibiting both nanocrystalline and nanoporous features. The resulting “bamboo-like” internal architecture comprises 30–50 nm grains and voids with similarly scaled pores. These geometrically tunable pillars, with diameters ranging from ~130 to 550 nm, serve as an ideal platform for probing deformation mechanisms in structurally heterogeneous metals at the nanoscale.

36 MATERIALS SCIENCE↗

Simulations of transition and turbulence on the Navier-Stokes computer

The Navier-Stokes Computer (NSC) consists of multiple local memory parallel processors interconnected in a hypercube network. Efficient implementation of algorithms on the NSC thus requires the effective utilization of both the coarse and fine grain paralelism inherent in the architectural design. The basic approach to implementing an algorithm on the NSC is presented herein. The particular finite-difference algorithm considered was developed for performing transition and turbulence simulations by direct solution of the time-dependent incompressible Navier-Stokes equations. The suitability of this algorithm for performing simulations of the isotropic turbulence problem is verified from computations performed on a Cray 2. Projected timing results for the algorithm on the NSC itself are presented for both the isotropic turbulence and laminar turbulent transition problems.

Krist, S. E.↗

The application of compiler-assisted multiple instruction retry to VLIW architectures

Very Long Instruction Word (VLIW) architectures enhance performance by exploiting fine-grained instruction level parallelism. We describe the development of two compiler assisted multiple instruction word retry schemes for VLIW architectures. The first scheme utilizes the compiler techniques previously developed for processors with single functional units. A compiler generated hazard-free code with different degrees of rollback capability for uniprocessors is compacted by a modified VLIW trace scheduling algorithm. Nops are then inserted in the scheduled code words to resolve data hazards for VLIW architectures. Performance is compared under three parameters: the rollback distance for uni-processors; the number of functional units; and the rollback distance for VLIW architectures. The second scheme employs a hardware read buffer to resolve frequently occurring data hazards, and utilizes the compiler to resolve the remaining hazards. Performance results are shown for six benchmark programs.

Chen, Shyh-Kwei↗