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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators

Next generation systems, such as edge devices, will have to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. This paper discusses the SODA synthesizer, an automated open source high-level ML framework-to-Verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets based on the LLVM infrastructure. The SODA synthesizers will allow implementing optimal designs by combining templated and fully tunable IPs and macros, and fully custom components generated through high-level synthesis. All these components will be provided through an extendable resource library, characterized with both commercial and open source logic design flows. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimension

Minutoli, Marco↗
DOE OSTI2019

Hardware MPI message matching: Insights into MPI matching behavior to inform design: Hardware MPI message matching

Here, this paper explores key differences of MPI match lists for several important United States Department of Energy (DOE) applications and proxy applications. This understanding is critical in determining the most promising hardware matching design for any given high-speed network. The results of MPI match list studies for the major open-source MPI implementations, MPICH and Open MPI, are presented, and we modify an MPI simulator, LogGOPSim, to provide match list statistics. These results are discussed in the context of several different potential design approaches to MPI matching–capable hardware. The data illustrate the requirements for different hardware designs in terms of performance and memory capacity. Finally, this paper's contributions are the collection and analysis of data to help inform hardware designers of common MPI requirements and highlight the difficulties in determining these requirements by only examining a single MPI implementation.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Hardware Design of a 1.7 kV SiC MOSFET Based MMC for Medium Voltage Motor Drives

Abstract—This paper presents the hardware design of a 7 kV dc bus,1 MVA, 0-1,000 Hz, 1.7 kV SiC MOSFET based medium voltage variable speed drive (MVVSD)1. The system is based on a 7-level three-phase modular multilevel converter (MMC). The full in-depth design, development, and testing of this prototype are provided, including MMC submodule development, arm inductor design, control hardware realization, system integration and thermal analysis. Finally, experimental results demonstrate the excellent performance of the 1.7 kV SiC MOSFET based submodule and the 1 MW, 7 kV MVVSD as a unity in various operation modes

SiC MOSFET, Modular Multilevel Converter, Medium V↗
DOE OSTI2026

PCA -BASED COMPRESSOR HARDWARE DESIGN GENERATOR IN CHISEL

SF-25-077 This repository includes a hardware generator written in Chisel that generates lossy compression hardware designs based on principal component analysis (PCA), along with a flexible testbench. It also includes a Python tool for evaluating the accuracy loss of integer quantization.

Kazutomo, Yoshi [Argonne National Laboratory (ANL)↗
DOE OSTI2018

Design and Assembly of SPT-3G Cold Readout Hardware

The third-generation upgrade to the receiver on the South Pole Telescope, SPT-3G, was installed at the South Pole during the 2016–2017 austral summer to measure the polarization of the cosmic microwave background. Increasing the number of detectors by a factor of 10 to ~16,000 required the multiplexing factor to increase to 68 and the bandwidth of the frequency-division readout electronics to span 1.6–5.2 MHz. This increase necessitates low-thermal conductance, low-inductance cryogenic wiring. Our cold readout system consists of planar thin-film aluminum inductive–capacitive resonators, wired in series with the detectors, summed together, and connected to 4K SQUIDs by 10-μm -thick niobium–titanium (NbTi) broadside-coupled striplines. Here, we present an overview of the cold readout electronics for SPT-3G, including assembly details and characterization of electrical and thermal properties of the system. We report, for the NbTi striplines, values of R≤10 -4 Ω , L=21±1 nH , and C=1.47±.02 nF . Additionally, the striplines’ thermal conductivity is described by kA=6.0±0.3 T 0.92±0.04 μW mm K -1 . Finally, we provide projections for cross talk induced by parasitic impedances from the stripline and find that the median value of percentage cross talk from leakage current is 0.22 and 0.09% from wiring impedance.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2021

Hardware Design of Medium Voltage SiC-Based Modular Multilevel Converters for Grid-Tied Applications

This paper presents a design of a 10 kV silicon carbide (SiC) MOSFET based modular multilevel converter (MMC). The MMC functions as the interconnection between a 24 kV dc bus and a 13. SkV distribution grid. This paper focuses on the hardware design of the MMC and its submodules. The gate driver, auxiliary power supply and bus bur in submodules are major components that need to meet high dv/dt immunity and high insulation voltage requirements. The gate driver achieves over 200 kV/us common mode transient immunity (CMTI). Its associated auxiliary power supply is based on an on-board transformer with over 30 kV insulation capability and 1.4 pF barrier capacitance. The busbar achieves less than 11 kV/cm electric field in the air to avoid partial discharges. Validation tests of the MMC submodule were performed by double pulse tests at 5 kV and buck converter tests at3 kV, 52A (peak). Reliable operations were achieved in validation tests.

auxiliary power supply↗
DOE OSTI2026

Multi-machine validation of plasma initiation modelling and prospects for future devices: Predicting plasma initiation using only hardware design and control room input data

This paper reports on the generic prediction capability of full electromagnetic plasma initiation modelling with DYON, which was carried out for the first time in fusion research by the joint modelling of the International Tokamak Physics Activity—Integrating Operation Scenario group. The following devices were included in the experiment database: VEST (spherical torus, copper coils, Stainless steel wall, R/a = 0.3 m/0.2 m, V v = 3.7 m 3 ), MAST-U (spherical torus, copper coils, C wall, R/a = 0.7 m/0.5 m, V v = 55 m 3 ), EAST (conventional tokamak, superconducting coils, metallic wall, R/a = 1.85 m/0.5 m, V v = 38 m 3 ), DIII-D (conventional tokamak, copper coils, C wall, R/a = 1.67 m/0.65 m, V v = 35 m 3 ), and KSTAR (conventional tokamak, superconducting coils, C wall, R/a = 1.8 m/0.5 m, V v = 55 m 3 ). Despite the different hardware features of the devices, the required operating spaces of the loop voltage induction and prefill gas pressure for inductive plasma initiation in each device were successfully reproduced by the predictive simulations with DYON using only the individual hardware design and the control room input data for each discharge. This successful validation across multiple machines demonstrates that the full electromagnetic DYON modelling can capture the essential physics of inductive plasma initiation. The simulation settings commonly employed for all modelling and the modifications necessary to account for the discrepancies between individual devices are reported. Predictions for ITER based on the multi-machine validation indicate that a wide range of prefill gas pressures exists for the Townsend breakdown and the plasma burn-through (0.01–1.5 mPa).

DYON↗
DOE OSTI2018

New Single Piece Blast Hardware design

W, Q and PF engineers and machinists designed and fabricated, on the new Mazak i300, the first Single Piece Blast Hardware (unclassified design shown) reducing fabrication and inspection time by over 50%. The first DU Single Piece is completed and will be used for Hydro Test 3680. Past hydro tests used a twopiece assembly due to a lack of equipment capable of machining the complex saddle shape in a single piece. The i300 provides turning and milling 5-axis machining on one machine. The milling head on the i300 can machine past 90 relative to the spindle axis. This makes it possible to machine the complex saddle surface on a single piece. Going to a single piece eliminates tolerance problems, such as tilting and eccentricity, that typically occurred when assembling the two pieces together

42 ENGINEERING↗
DOE OSTI2022

Prototype hardware design and testing of the global common module for the global trigger subsystem of the ATLAS phase-II upgrade

We report the High-Luminosity Large Hadron Collider (HL-LHC) will deliver more than ten times the integrated luminosity of the previous runs combined. Meeting its stricter throughput requirements poses new challenges to the Trigger and Data Acquisition (TDAQ) systems of the LHC experiments. Introduced in the framework of the ATLAS experiment’s HL upgrade, the Global Trigger (GT) is a new subsystem which will perform offline-like algorithms on full-granularity calorimeter data. The implementation of the GT’s functionality is firmware-focused and is composed of three layers: multiplexing (or data aggregating), global event processing, and demultiplexing interface to the central trigger processor. Each layer will be composed of several, similar nodes, hosted on replicas of identical hardware, the Global Common Module (GCM), an ATCA front board which is designed to be adopted throughout the entire GT subsystem. This article proceeds from the TWEPP 2021 conference and presents the GCM hardware design, performed in 2020, and focuses on some key results of its extensive testing performed in 2021.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Hardware design and testing of the generic rear transition module for the global trigger subsystem of ATLAS Phase-II Upgrade

Abstract In the framework of the ATLAS experiment’s Phase-II Upgrade at the High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 μs-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. The implementation of the functionality is firmware-focused and composed of several processing nodes, which are hosted on identical hardware, made up of an Advanced Telecommunications Computing Architecture (ATCA) front board, called Global Common Module (GCM), and a rear transition module (RTM), called Generic RTM (GRM). The GRM, which was developed to mitigate the risks deriving from the complex design and power management of the GCM, features an advanced Xilinx Versal Prime system-on-chip and can handle communication with the GCM and Front-End Link eXchange (FELIX) subsystem and trigger processors through 124 25.8 Gb/s transceiver links, for readout and control. Additionally, the GRM mounts a Low-Power GigaBit Transceiver (lpGBT) chip which enables emulation of the detector front-ends for integration tests. This paper presents the GRM hardware design and its testing.

Instruments & Instrumentation↗
DOE OSTI2020

Hardware Design and Demonstration of a 100kW, 99% Efficiency Dual Active Half Bridge Converter Based on 1700V SiC Power MOSFET

High efficiency, high density and galvanically isolated power converters are attractive for numerous medium voltage high power applications. This paper presents a 1.5kVdc, 100kW bidirectional Dual Active Half Bridge (DAHB) using newly developed 1.7kV SiC MOSFET modules. The DAHB achieved an efficiency of 98.6% at full load of 100kW and a maximum of 99% at 45kW, operating as an isolated DC/DC converter. The converter also achieved an efficiency of 97.8% operating as an isolated DC/AC inverter. An optimized PCB-based busbar design has significantly reduced the voltage overshoot across the device, making the design suitable for 1500Vdc input application such as 1500V PV inverters. Typical partial discharge inception voltage (PDIV) of the optimized PCB busbar is 1.7kVpeak with total charge <10pC. The power density of the DAHB converter is 1.8MVA/m 3 which is much higher than traditional two-stage industry products. The DAHB converter can be used as a building block for a 4.16kV/1MVA utility scale PV systems with input parallel and output series configuration.

Xu, Wei↗
DOE OSTI2019

Telemetry and H-Gear Engineering Hardware Design and Delivery Standards

Telemetry and H-Gear Engineering, Org. 8430, is frequently required to design, manufacture, test, and deliver products directly to flight tests and important ground tests. Due to schedule or budget constraints, these deliveries often cannot follow the full product acceptance process laid out in Sandia's Realize Product Processes. Telemetry and H-Gear Engineering therefore created tailored quality expectations and outputs for products that fall into this category. This document describes these quality requirements and the reasons they have been put in place.

42 ENGINEERING↗