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NASA NTRS2010

Photon Counting Using Edge-Detection Algorithm

New applications such as high-datarate, photon-starved, free-space optical communications require photon counting at flux rates into gigaphoton-per-second regimes coupled with subnanosecond timing accuracy. Current single-photon detectors that are capable of handling such operating conditions are designed in an array format and produce output pulses that span multiple sample times. In order to discern one pulse from another and not to overcount the number of incoming photons, a detection algorithm must be applied to the sampled detector output pulses. As flux rates increase, the ability to implement such a detection algorithm becomes difficult within a digital processor that may reside within a field-programmable gate array (FPGA). Systems have been developed and implemented to both characterize gigahertz bandwidth single-photon detectors, as well as process photon count signals at rates into gigaphotons per second in order to implement communications links at SCPPM (serial concatenated pulse position modulation) encoded data rates exceeding 100 megabits per second with efficiencies greater than two bits per detected photon. A hardware edge-detection algorithm and corresponding signal combining and deserialization hardware were developed to meet these requirements at sample rates up to 10 GHz. The photon discriminator deserializer hardware board accepts four inputs, which allows for the ability to take inputs from a quadphoton counting detector, to support requirements for optical tracking with a reduced number of hardware components. The four inputs are hardware leading-edge detected independently. After leading-edge detection, the resultant samples are ORed together prior to deserialization. The deserialization is performed to reduce the rate at which data is passed to a digital signal processor, perhaps residing within an FPGA. The hardware implements four separate analog inputs that are connected through RF connectors. Each analog input is fed to a high-speed 1-bit comparator, which digitizes the input referenced to an adjustable threshold value. This results in four independent serial sample streams of binary 1s and 0s, which are ORed together at rates up to 10 GHz. This single serial stream is then deserialized by a factor of 16 to create 16 signal lines at a rate of 622.5 MHz or lower for input to a high-speed digital processor assembly. The new design and corresponding hardware can be employed with a quad-photon counting detector capable of handling photon rates on the order of multi-gigaphotons per second, whereas prior art was only capable of handling a single input at 1/4 the flux rate. Additionally, the hardware edge-detection algorithm has provided the ability to process 3-10 higher photon flux rates than previously possible by removing the limitation that photoncounting detector output pulses on multiple channels being ORed not overlap. Now, only the leading edges of the pulses are required to not overlap. This new photon counting digitizer hardware architecture supports a universal front end for an optical communications receiver operating at data rates from kilobits to over one gigabit per second to meet increased mission data volume requirements.

Gin, Jonathan W.↗

NASA NTRS1992

Digital tracking loops for a programmable digital modem

In this paper, an analysis and hardware emulation of the tracking loops for a very flexible programmable digital modem (PDM) will be presented. The modem is capable of being programmed for 2, 4, 8, 16-PSK, 16-QAM, MSK, and Offset-QPSK modulation schemes over a range of data rates from 2.34 to 300 Mbps with programmable spectral occupancy from 1.2 to 1.8 times the symbol rate; these operational parameters are executable in burst or continuous mode. All of the critical processing in both the modulator and demodulator is done at baseband with very high-speed digital hardware and memory. Quadrature analog front-ends are used for translation between baseband and the IF center frequency. The modulator is based on a table lookup approach, where precomputed samples are stored in memory and clocked out according to the incoming data pattern. The sample values are predistorted to counteract the effects of the other filtering functions in the link as well as any transmission impairments. The demodulator architecture was adapted from a joint estimator-detector (JED) mathematical analysis. Its structure is applicable to most signalling formats that can be represented in a two-dimensional space. The JED realization uses interdependent, mutually aiding tracking loops with post-detection data feedback. To expedite and provide for more reliable synchronization, initial estimates for these loops are computed in a parallel acquisition processor. The cornerstone of the demodulator realization is the pre-averager received data filter which allows operation over a broad range of data rates without any hardware changes and greatly simplifies the implementation complexity. The emulation results confirmed tracking loop operation over the entire range of operational parameters listed above, as well as the capability of achieving and maintaining synchronization at BER's in excess of 10(exp -1). The emulation results also showed very close agreement with the tracking loop analysis, and validated the resolution apportionment of the various hardware elements in the tracking loops.

Poklemba, John J.↗

NASA NTRS2003

A Scintillation Counter System Design To Detect Antiproton Annihilation using the High Performance Antiproton Trap(HiPAT)

The High Performance Antiproton Trap (HiPAT), a system designed to hold up to l0(exp 12) charge particles with a storage half-life of approximately 18 days, is a tool to support basic antimatter research. NASA's interest stems from the energy density represented by the annihilation of matter with antimatter, 10(exp 2)MJ/g. The HiPAT is configured with a Penning-Malmberg style electromagnetic confinement region with field strengths up to 4 Tesla, and 20kV. To date a series of normal matter experiments, using positive and negative ions, have been performed evaluating the designs performance prior to operations with antiprotons. The primary methods of detecting and monitoring stored normal matter ions and antiprotons within the trap includes a destructive extraction technique that makes use of a micro channel plate (MCP) device and a non-destractive radio frequency scheme tuned to key particle frequencies. However, an independent means of detecting stored antiprotons is possible by making use of the actual annihilation products as a unique indicator. The immediate yield of the annihilation event includes photons and pie mesons, emanating spherically from the point of annihilation. To "count" these events, a hardware system of scintillators, discriminators, coincident meters and multi channel scalars (MCS) have been configured to surround much of the HiPAT. Signal coincidence with voting logic is an essential part of this system, necessary to weed out the single cosmic ray events from the multi-particle annihilation shower. This system can be operated in a variety of modes accommodating various conditions. The first is a low-speed sampling interval that monitors the background loss or "evaporation" rate of antiprotons held in the trap during long storage periods; provides an independent method of validating particle lifetimes. The second is a high-speed sample rate accumulating information on a microseconds time-scale; useful when trapped antiparticles are extracted against a target, providing an indication of quantity. This paper details the layout of this system, setup of the hardware components around HiPAT, and applicable checkouts using normal matter radioactive sources.

Martin, James J.↗

NASA NTRS2009

Structured Low-Density Parity-Check Codes with Bandwidth Efficient Modulation

In this work, we study the performance of structured Low-Density Parity-Check (LDPC) Codes together with bandwidth efficient modulations. We consider protograph-based LDPC codes that facilitate high-speed hardware implementations and have minimum distances that grow linearly with block sizes. We cover various higher- order modulations such as 8-PSK, 16-APSK, and 16-QAM. During demodulation, a demapper transforms the received in-phase and quadrature samples into reliability information that feeds the binary LDPC decoder. We will compare various low-complexity demappers and provide simulation results for assorted coded-modulation combinations on the additive white Gaussian noise and independent Rayleigh fading channels.

Crew Exploration Vehicle (CEV)↗

NASA NTRS1978

Processing laser velocimeter high-speed burst counter data

The statistical calculations of the mean and potential bias errors are considered with respect to their applicability to the randomly sampled velocity data obtained from a laser velocimeter. Techniques for displaying the resulting data in the form of arrow plots, flow streamline plots, and contour maps are also discussed. A description is presented of the operation of a new hardware interface between the signal processing electronics and the computer. The interface has been constructed to make it possible to use recently developed data processing techniques for obtaining turbulent power spectra from laser velocimeter data. Additional capabilities which were built into the interface allow the measurement of the velocity vector for each particle passing through the laser velocimeter sample window. By processing the data with extended versions of the turbulent power spectra techniques, cross spectra, interactions between velocity magnitude fluctuations, and flow angle fluctuations may be investigated.

Meyers, J. F.↗

NASA NTRS1982

Digital TV tri-state delta modulation system for Space Shuttle ku-band downlink

A tri-state delta modulation/demodulation (TSDM) technique which provides for efficient run-length coding of constant-intensity segments of a TV picture is described. Aspects of the hardware implementation of a high-speed TSDM transmitter and receiver for black-and-white TV or field-sequential color or NTSC format color are reviewed. Run-length encoding of the TSDM output can consistently reduce the required channel data rate well below one bit per sample. As compared with a bistate delta modulation system, the present technique eliminates granularity in the reconstructed video without degrading rise or fall times. About 40 chips are used by TSDM when used to handle the luminance information in a color link. A possible overall space and ground functional configuration to accommodate Shuttle digital TV with scrambling for privacy is presented.

Udalov, S.↗

NASA NTRS2006

Summary of Stirling Convertor Testing at NASA Glenn Research Center

The NASA Glenn Research Center (GRC) has been testing free-piston Stirling convertors for potential use in radioisotope power systems. These convertors tend to be in the 35 to 80 W electric power output range. Tests at GRC have accumulated over 80,000 hr of operation. Test articles have been received from Infinia Corporation of Kennewick, Washington and from Sunpower of Athens, Ohio. Infinia designed and built the developmental Stirling Technology Demonstration Convertors (TDC) in addition to the more advanced Test Bed and Engineering Unit convertors. GRC has eight of the TDC's under test including two that operate in a thermal vacuum environment. Sunpower designed and developed the EE-35 and the Advanced Stirling Convertor (ASC). GRC has six of the EE- 35 s and is preparing for testing multiple ASC s. Free-piston Stirling convertors for radioisotope power systems make use of non-contacting operation that eliminates wear and is suited for long-term operation. Space missions with radioisotope power systems are often considered that extend from three to 14 years. One of the key capabilities of the GRC test facility is the ability to support continuous, unattended operation. Hardware, software, and procedures for preparing the test articles were developed to support these tests. These included the processing of the convertors for minimizing the contaminants in the working fluid, developing a helium charging system for filling and for gas sample analysis, and the development of new control software and a high-speed protection circuit to insure safe, round-the-clock operation. Performance data of Stirling convertors over time is required to demonstrate that a radioisotope power system is capable of providing reliable power for multi-year missions. This paper will discuss the status of Stirling convertor testing at GRC.

Schreiber, Jeffrey G.↗

NASA NTRS2006

Summary of Stirling Convertor Testing at GRC

The NASA Glenn Research Center (GRC) has been testing free-piston Stirling convertors for potential use in radioisotope power systems. These convertors tend to be in the 35 to 80 watt electric power output range. Tests at GRC have accumulated over 80,000 hours of operation. Test articles have been received from Infinia Corporation of Kennewick, WA and from Sunpower of Athens, OH. Infinia designed and built the developmental Stirling Technology Demonstration Convertors (TDC) in addition to the more advanced Test Bed and Engineering Unit convertors. GRC has eight of the TDC's under test including two that operate in a thermal vacuum environment. Sunpower designed and developed the EE- 35 and the Advanced Stirling Convertor (ASC). GRC has six of the EE-35's and is preparing for testing multiple ASC's. Free-piston Stirling convertors for radioisotope power systems make use of non-contacting operation that eliminates wear and is suited for longterm operation. Space missions with radioisotope power systems are often considered that extend from three to 14 years. One of the key capabilities of the GRC test facility is the ability to support continuous, unattended operation. Hardware, software, and procedures for preparing the test articles were developed to support these tests. These included the processing of the convertors for minimizing the contaminants in the working fluid, developing a helium charging system for filling and for gas sample analysis, and the development of new control software and a high-speed protection circuit to insure safe, round-the-clock operation. Performance data of Stirling convertors over time is required to demonstrate that a radioisotope power system is capable of providing reliable power for multi-year missions. This paper will discuss the status of Stirling convertor testing at GRC.

Schreiber, Jeffrey G.↗

NASA NTRS1989

Queuing theory models for computer networks

A set of simple queuing theory models which can model the average response of a network of computers to a given traffic load has been implemented using a spreadsheet. The impact of variations in traffic patterns and intensities, channel capacities, and message protocols can be assessed using them because of the lack of fine detail in the network traffic rates, traffic patterns, and the hardware used to implement the networks. A sample use of the models applied to a realistic problem is included in appendix A. Appendix B provides a glossary of terms used in this paper. This Ames Research Center computer communication network is an evolving network of local area networks (LANs) connected via gateways and high-speed backbone communication channels. Intelligent planning of expansion and improvement requires understanding the behavior of the individual LANs as well as the collection of networks as a whole.

Galant, David C.↗

NASA NTRS1976

Test data from small solid propellant rocket motor plume measurements (FA-21)

A program is described for obtaining a reliable, parametric set of measurements in the exhaust plumes of solid propellant rocket motors. Plume measurements included pressures, temperatures, forces, heat transfer rates, particle sampling, and high-speed movies. Approximately 210,000 digital data points and 15,000 movie frames were acquired. Measurements were made at points in the plumes via rake-mounted probes, and on the surface of a large plate impinged by the exhaust plume. Parametric variations were made in pressure altitude, propellant aluminum loading, impinged plate incidence angle and distance from nozzle exit to plate or rake. Reliability was incorporated by continual use of repeat runs. The test setup of the various hardware items is described along with an account of test procedures. Test results and data accuracy are discussed. Format of the data presentation is detailed. Complete data are included in the appendix.

Hair, L. M.↗

NASA NTRS1991

Advanced techniques and technology for efficient data storage, access, and transfer

Advanced techniques for efficiently representing most forms of data are being implemented in practical hardware and software form through the joint efforts of three NASA centers. These techniques adapt to local statistical variations to continually provide near optimum code efficiency when representing data without error. Demonstrated in several earlier space applications, these techniques are the basis of initial NASA data compression standards specifications. Since the techniques clearly apply to most NASA science data, NASA invested in the development of both hardware and software implementations for general use. This investment includes high-speed single-chip very large scale integration (VLSI) coding and decoding modules as well as machine-transferrable software routines. The hardware chips were tested in the laboratory at data rates as high as 700 Mbits/s. A coding module's definition includes a predictive preprocessing stage and a powerful adaptive coding stage. The function of the preprocessor is to optimally process incoming data into a standard form data source that the second stage can handle.The built-in preprocessor of the VLSI coder chips is ideal for high-speed sampled data applications such as imaging and high-quality audio, but additionally, the second stage adaptive coder can be used separately with any source that can be externally preprocessed into the 'standard form'. This generic functionality assures that the applicability of these techniques and their recent high-speed implementations should be equally broad outside of NASA.

Rice, Robert F.↗

NASA NTRS2012

High-Speed, Multi-Channel Serial ADC LVDS Interface for Xilinx Virtex-5 FPGA

Analog-to-digital converters (ADCs) are used in scientific and communications instruments on all spacecraft. As data rates get higher, and as the transition is made from parallel ADC designs to high-speed, serial, low-voltage differential signaling (LVDS) designs, the need will arise to interface these in field programmable gate arrays (FPGAs). As Xilinx has released the radiation-hardened version of the Virtex-5, this will likely be used in future missions. High-speed serial ADCs send data at very high rates. A de-serializer instantiated in the fabric of the FPGA could not keep up with these high data rates. The Virtex-5 contains primitives designed specifically for high-speed, source-synchronous de-serialization, but as supported by Xilinx, can only support bitwidths of 10. Supporting bit-widths of 12 or more requires the use of the primitives in an undocumented configuration, a non-trivial task. A new SystemVerilog design was written that is simpler and uses fewer hardware resources than the reference design described in Xilinx Application Note XAPP866. It has been shown to work in a Xilinx XC5VSX24OT connected to a MAXIM MAX1438 12-bit ADC using a 50-MHz sample clock. The design can be replicated in the FPGA for multiple ADCs (four instantiations were used for a total of 28 channels).

Taylor, Gregory H.↗

NASA NTRS1983

Experimental study using Nearfield Acoustical Holography of sound transmission fuselage sidewall structures

This project involves the development of the Nearfield Acoustic Holography (NAH) technique (in particular its extension from single frequency to wideband noise measurement) and its application in a detailed study of the noise radiation characteristics of several samples of aircraft sidewall panels. With the extensive amount of information provided by the NAH technique, the properties of the sound field radiated by the panels may be correlated with their structure, mounting, and excitation (single frequency or wideband, spatially correlated or uncorrelated, structure-borne). The work accomplished at the beginning of this grant period included: (1) Calibration of the 256 microphone array and test of its accuracy. (2) extension of the facility to permit measurements on wideband noise sources. The extensions incuded the addition of high-speed data acquisition hardware and an array processor, and the development of new software. (3) Installation of motion picture graphics for correlating panel motion with structure, mounting, radiation, etc. (4) Development of new holographic data processing techniques.

Maynard, J. D.↗

NASA NTRS1989

An experimental investigation of a low Reynolds number turbulent boundary layer subject to an adverse pressure gradient

A very low Reynolds number turbulent boundary layer subject to an adverse pressure gradient is studied. The aim is to obtain highly accurate mean-flow and turbulence measurements under conditions that can be closely related to the numerical simulations of Philippe Spalart for the purposes of CFD validation. Much of the Boundary Layer Wind Tunnel was completely rebuilt with a new wider contraction and working section which will improve compatibility with the simulations. A unique sophisticated high-speed computer controlled 3-D probe traversing mechanism was integrated into the test section. Construction of the tunnel and traverse is discussed in some detail. The hardware is now complete, and measurements are in progress. The mean-flow data indicate that a suitably two-dimensional base flow was established. Automation of the probe positioning and data acquistion have led to a decreased running time for total pressure measurements. However, the most significant benefits are expected to occur when using hot-wire probes. Calibrations can be performed automatically and there is no need to handle fragile probes when moving between measuring stations. Techniques are being developed which require sampling of the signals from moving hot-wire probes on the basis of their position in the flow. Measurements can be made in high intensity turbulence by flying probes upstream at high speed so that the relative magnitude of the turbulent velocity fluctuations are reduced. In regions, where the turbulence intensity is not too large, the probe can also be repetitively scanned across very dense spatial grids in other directions. With this technique, a complete profile can be measured in about 1/3 the time and with a spatial density about 50 times that obtainable using a stationary probe.

Watmuff, Jonathan H.↗

NASA NTRS1983

A high-speed implementation of the random decrement algorithm

The algorithm is useful for measuring net system damping levels in stochastic processes and for the development of equivalent linearized system response models. The algorithm works by summing together all subrecords which occur after predefined threshold level is crossed. The random decrement signature is normally developed by scanning stored data and adding subrecords together. The high speed implementation of the random decrement algorithm exploits the digital character of sampled data and uses fixed record lengths of 2(n) samples to greatly speed up the process. The contributions to the random decrement signature of each data point was calculated only once and in the same sequence as the data were taken. A hardware implementation of the algorithm using random logic is diagrammed and the process is shown to be limited only by the record size and the threshold crossing frequency of the sampled data. With a hardware cycle time of 200 ns and 1024 point signature, a threshold crossing frequency of 5000 Hertz can be processed and a stably averaged signature presented in real time.

Kiraly, L. J.↗

NASA NTRS1993

Algorithms for high-speed universal noiseless coding

This paper provides the basic algorithmic definitions and performance characterizations for a high-performance adaptive noiseless (lossless) 'coding module' which is currently under separate developments as single-chip microelectronic circuits at two NASA centers. Laboratory tests of one of these implementations recently demonstrated coding rates of up to 900 Mbits/s. Operation of a companion 'decoding module' can operate at up to half the coder's rate. The functionality provided by these modules should be applicable to most of NASA's science data. The hardware modules incorporate a powerful adaptive noiseless coder for 'standard form' data sources (i.e., sources whose symbols can be represented by uncorrelated nonnegative integers where the smaller integers are more likely than the larger ones). Performance close to data entries can be expected over a 'dynamic range' of from 1.5 to 12-15 bits/sample (depending on the implementation). This is accomplished by adaptively choosing the best of many Huffman equivalent codes to use on each block of 1-16 samples. Because of the extreme simplicity of these codes no table lookups are actually required in an implementation, thus leading to the expected very high data rate capabilities already noted.

Rice, Robert F.↗

NASA NTRS2003

Reliable Transport over SpaceWire for James Webb Space Telescope (JWST) Focal Plane Electronics (FPE) Network

NASA's James Webb Space Telescope (JWST) faces difficult technical and budgetary challenges to overcome before it is scheduled launch in 2010. The Integrated Science Instrument Module (ISIM), shares these challenges. The major challenge addressed in this paper is the data network used to collect, process, compresses and store Infrared data. A total of 114 Mbps of raw information must be collected from 19 sources and delivered to the two redundant data processing units across a twenty meter deployed thermally restricted interface. Further data must be transferred to the solid-state recorder and the spacecraft. The JWST detectors are kept at cryogenic temperatures to obtain the sensitivity necessary to measure faint energy sources. The Focal Plane Electronics (FPE) that sample the detector, generate packets from the samples, and transmit these packets to the processing electronics must dissipate little power in order to help keep the detectors at these cold temperatures. Separating the low powered front-end electronics from the higher-powered processing electronics, and using a simple high-speed protocol to transmit the detector data minimize the power dissipation near the detectors. Low Voltage Differential Signaling (LVDS) drivers were considered an obvious choice for physical layer because of their high speed and low power. The mechanical restriction on the number cables across the thermal interface force the Image packets to be concentrated upon two high-speed links. These links connect the many image packet sources, Focal Plane Electronics (FPE), located near the cryogenic detectors to the processing electronics on the spacecraft structure. From 12 to 10,000 seconds of raw data are processed to make up an image, various algorithms integrate the pixel data Loss of commands to configure the detectors as well as the loss of science data itself may cause inefficiency in the use of the telescope that are unacceptable given the high cost of the observatory. This combination of requirements necessitates a redundant, fault tolerant, high- speed, low mass, low power network with a low Bit error Rate(1E-9- 1E-12). The ISIM systems team performed many studies of the various network architectures that meeting these requirements. The architecture selected uses the Spacewire protocol, with the addition of a new transport and network layer added to implement end-to-end reliable transport. The network and reliable transport mechanism must be implemented in hardware because of the high average information rate and the restriction on the ability of the detectors to buffer data due to power and size restrictions. This network and transport mechanism was designed to be compatible with existing Spacewire links and routers so that existing equipment and designs may be leveraged upon. The transport layer specification is being coordinated with European Space Agency (ESA), Spacewire Working Group and the Consultative Committee for Space Data System (CCSDS) PlK Standard Onboard Interface (SOIF) panel, with the intent of developing a standard for reliable transport for Spacewire. Changes to the protocol presented are likely since negotiations are ongoing with these groups. A block of RTL VHDL that implements a multi-port Spacewire router with an external user interface will be developed and integrated with an existing Spacewire Link design. The external user interface will be the local interface that sources and sinks packets onto and off of the network (Figure 3). The external user interface implements the network and transport layer and handles acknowledgements and re-tries of packets for reliable transport over the network. Because the design is written in RTL, it may be ported to any technology but will initially be targeted to the new Actel Accelerator series (AX) part. Each link will run at 160 Mbps and the power will be about 0.165 Watt per link worst case in the Actel AX.

Rakow, Glenn↗

NASA NTRS2003

The Data Acquisition and Controls Systems (DACS) of the E-Complex at the John C. Stennis Space Center, MS: A General Overview

The John C. Stennis Space Center (SSC) provides test operations services to a variety of customers including NASA, DoD, commercial enterprises, and others for the development of current next-generation rocket propulsion systems. Many of these test operations services are provided in the E-Complex series of test facilities. The E-Complex is composed of three active test stands (E1, E2, & E3), each with two or more test positions. Each test position is comprised of unique sets of data acquisition and controls hardware and software that record both facility and test article data and safely operate the test facility. The E-Complex data acquisition system (DAS) is actually composed of two separate systems, one for static data and the other for dynamic. The static DAS, otherwise known as the Low-Speed DAS (LSDAS), samples 16 bit data at 250 samples-per-second (SPS), although an aggregate sample rate of 200,000 SPS is possible. The dynamic data acquisition system, otherwise known as the high-speed DAS (HSDAS), samples 16 bit data at 100K SPS with a 45 KHz bandwidth.

Hughes, Mark S.↗