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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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Solid-State Transformer and Hybrid Transformer With Integrated Energy Storage in Active Distribution Grids: Technical and Economic Comparison, Dispatch, and Control

Solid-state transformer (SST) and hybrid transformer (HT) are promising alternatives to the line-frequency transformer (LFT) in smart grids. The SST features medium-frequency isolation, full controllability for voltage regulation, reactive power compensation, and the capability of battery energy storage system (BESS) integration with multiport configuration. The HT has a partially-rated converter for fractional controllability and can integrate a small BESS. Fast grid-edge voltage fluctuations from increased solar photovoltaic (PV) and electric vehicle (EV) penetration are difficult to manage for mechanical load tap changers. Hence, along with the trend towards more BESS in the grid, the controllability and the storage integration capability of the SST and HT are of strong interest. However, a review of literature shows existing SST and HT research is mostly at converter level, while system-level assessments are scarce. Assessing technical and economic impacts is critical to understanding the benefits and role of the SST and HT to guide future research, which is presented for the first time in this article. Experimental results from medium-voltage (MV) SST and MV HT prototypes are shown to confirm equipment-level feasibility, where the voltage controllability waveforms of a MV HT prototype are reported for the first time. Comparative simulations are performed on a modified IEEE 34-bus system. Here, a grid-model-less decentralized grid-edge voltage control method and a day-ahead BESS dispatch method are proposed for the SST and HT. The simulations show that the SST and HT with integrated storage can host more PV, achieve peak shaving, mitigate voltage fluctuation and reverse power flow, and support energy arbitrage for operational cost reduction, as compared to the LFT. Moreover, comprehensive analyses of net present value (NPV) and internal rate of return (IRR) are performed under different installed PV capacities, HT’s partial converter ratings, and BESS capacities. Sensitivities to future cost reductions of the PV and BESS are studied. Although the NPV and IRR are currently negative, 60% capital cost reduction or 150% revenue increase will make the SST and HT economically viable in the use case studied.

14 SOLAR ENERGY↗

Advanced Signal Processing for High Temperatures Health Monitoring of Condensed Water Height in Steam Pipes

An advanced signal processing methodology is being developed to monitor the height of condensed water thru the wall of a steel pipe while operating at temperatures as high as 250deg. Using existing techniques, previous study indicated that, when the water height is low or there is disturbance in the environment, the predicted water height may not be accurate. In recent years, the use of the autocorrelation and envelope techniques in the signal processing has been demonstrated to be a very useful tool for practical applications. In this paper, various signal processing techniques including the auto correlation, Hilbert transform, and the Shannon Energy Envelope methods were studied and implemented to determine the water height in the steam pipe. The results have shown that the developed method provides a good capability for monitoring the height in the regular conditions. An alternative solution for shallow water or no water conditions based on a developed hybrid method based on Hilbert transform (HT) with a high pass filter and using the optimized windowing technique is suggested. Further development of the reported methods would provide a powerful tool for the identification of the disturbances of water height inside the pipe.

health monitoring↗

Large CMOS imager using hadamard transform based multiplexing

We have developed a concept design for a large (~10k x 10k) CMOS imaging array whose elements are grouped in small subarrays with N pixels in each. The subarrays are code-division multiplexed using the Hadamard Transform (HT) based encoding. The Hadamard code improves the signal-to-noise (SNR) ratio to the reference of the read-out amplifier by a factor of N^1/2. This way of grouping pixels reduces the number of hybridization bumps by N. A single chip layout has been designed and the architecture of the imager has been developed to accommodate the HT base multiplexing into the existing CMOS technology. The imager architecture allows for a trade-off between the speed and the sensitivity. The envisioned imager would operate at a speed >100 fps with the pixel noise < 20 e-. The power dissipation would be ~100 pW/pixe1. The combination of the large format, high speed, high sensitivity and low power dissipation can be very attractive for space reconnaissance applications.

CMOS imager↗