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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Estimation, Minimization, and Validation of Commutation Loop Inductance for a 135-kW SiC EV Traction Inverter

With growing interests in low inductance SiC based power module packaging, it is vital to focus on system level design aspects to facilitate easy integration of the modules and reap system level benefits. To effectively utilize the low inductance modules, busbar and interconnects should also be designed with low stray inductances. A wholistic investigation of the flux path and flux cancellations in the module-busbar assembly which as differentially coupled series inductors is thus mandatory for a system level design. This work presents a busbar design which can be adopted to effectively integrate the CREE’s low inductance 1.2 kV/1.7 kV SiC power modules. The paper also proposes a novel measurement technique to measure the inductance of the modulebusbar assembly as a whole rather than deducing it from individual components. The inductance of the overall commutation loop of the inverter which encompasses the SiC power module, interconnects and PCB busbar have been estimated using finite element analysis (FEA). Furthermore, insights gained from FEA provided the guidelines to decide on the placement of the decoupling capacitors in the busbar to minimize the overall commutation loop inductance from 12.8 nH to 7.4 nH which resulted in significant reduction in the device voltage overshoot. The simulation results have been validated through measurements using an impedance analyzer with less than 5% difference between extracted loop inductance from FEA and measurements. The bus bar design study and the measurement technique discussed in this paper, can be easily extended to other power module packages. Finally, the 135 kW inverter has been compared to a similar highpower inverter utilizing a laminated busbar to highlight the performance of the former.

42 ENGINEERING↗
DOE OSTI2024

Stacked-Die SiC Half-Bridge Module with Minimum Loop Inductance

Minimizing parasitic inductance of power modules is needed to advance their electrical performance. Innovation in the past decade has driven down the inductance of SiC half-bridge power modules to around 1–2 nH by using multilayer, embedded, and hybrid structures. Further reduction becomes difficult, mainly limited by the excessive interconnects required for the planar placement of vertical conducting chips. To address this, a vertically stacked-die approach is proposed in this paper, taking advantage of the vertical conducting nature of the SiC chips. With ceramic decoupling capacitors integrated, 0.48 nH overall loop inductance is achieved and validated by experimental measurement. This paper also discusses potential approaches to further reduce the inductance.

Ribeiro, Pedro↗
DOE OSTI2025

3D Multiphysics Model for Large Scale Planar Cell: Inductance Investigation in Impedance Analysis

Developed a comprehensive 3D multiphysics model to analyze impedance behavior in large-scale planar Solid Oxide Fuel Cells (SOFCs). The model investigates how impedance varies across operating conditions and cell components, with a particular focus on inductive loops or negative capacitance at the air electrode. It was found that the Inductive loop disappears in the low-frequency zone when the activation overpotential or faradic current is not temperature-dependent. These findings offer new insights into SOFC impedance behavior.

impedence analysis↗
DOE OSTI2022

A PCB-Embedded 1.2 kV SiC MOSFET Half-Bridge Package for a 22 kW AC–DC Converter

This article presents the design and analysis of a double-side-cooled printed circuit board (PCB) embedded silicon carbide (SiC) MOSFET half-bridge package with low loop inductances and an integrated gate driver. The 1.2 kV SiC MOSFET dies used in the half-bridge package are embedded in the PCB using AT&S's patented technique. The dies are cooled and electrically connected to traces in the PCB through copper-filled microvias. The design methodology accounts for both electrical and thermal performance, limiting the power-loop inductance to 2.3 nH and the maximum package temperature to less than the 175 °C limit. The integration of the gate drive circuitry allows for a high power density and 2.2 nH gate-loop inductances. At 0.12 K/W, the measured junction-to-case thermal resistance with double-sided cooling is 57% lower than that of a TO-247 package. Under similar operating conditions, the PCB-embedded half-bridge package also achieves a 5.6 times lower voltage overshoot and a 0.5% higher peak efficiency than a TO-247-based half-bridge. This article reports the first demonstration of PCB-embedded 1.2 kV SiC MOSFET packages in buck, boost, and ac–dc converters. Furthermore, the prototype three-phase ac–dc converter for an electric vehicle on-board charger is composed of six PCB-embedded half-bridge packages and achieves an efficiency of 98.2% and a power density of 182 W/in 3 .

42 ENGINEERING↗
DOE OSTI2025

Packaging a 650V/400A GaN Half-bridge Power Module with Ultra-low Parasitics for Electric Vehicle Drive Applications

This paper proposes a compact and efficient half-bridge power module with three 650 V / 150 A GaN dies in parallel. The power module incorporates a main power printed circuit board (PCB), an interface PCB, and a flex PCB to achieve low parasitics in both power loop and gate-side connection, resolving the issue of high parasitics typically encountered with wire bonding in high-current applications. Additionally, the interface PCB decouples the design constraints between the power loop and the gate loops. The proposed design is optimized with a vertical loop configuration to reduce power loop inductance through magnetic flux cancellation. Finite element analysis indicates that the power loop inductance is 0.58 nH at 100 MHz, while the maximum die junction temperature reaches 131 °C under an ambient temperature of 65 °C and a load current of 385 A. The proposed multi-piece PCB structure reduces the inductance of the drive circuit to minimize EMI and to mitigate false triggering. At the same time, it reduces impedance mismatches across different driver circuits, thereby achieving dynamic current sharing in multi-chip parallel configurations. Under simulation conditions of 400 V / 385 A, the current imbalance among chips was limited to 5 A. A 400 V / 385 A double-pulse test was conducted to experimentally validate the performance of the proposed power module.

30 DIRECT ENERGY CONVERSION↗
DOE OSTI2025

Rapid Prototyping Techniques for Organic Direct-Bonded-Copper Power Modules

Organic Direct-Bonded-Copper (ODBC) is a novel packaging technology for power modules which allows higher flexibility in layout design. In this work, a set of rapid prototyping techniques are developed for ODBC modules based on a polyimide dielectric material. These techniques enable fast and low-cost fabrication of modules with 3-Dimensional (3D) layout features. An example half-bridge (HB) silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) module is designed and prototyped using the proposed techniques aiming at ultra-low power loop inductance. Finite element analysis (FEA)-circuit co-simulations results and experimental results validate an approximately 0.71nH power loop inductance for the example module design.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Estimation of Arrivals on Green at Signalized Intersections Using Stop-Bar Video Detection

Across the world, traffic congestion is increasing with alarming rapidity. Traffic signal control effectiveness, in coordinated networks, is often investigated in relation to the type of vehicle arrivals at the signalized intersections. Recently, several transportation agencies have switched from traditional loop detectors to video detection. When video cameras are accompanied by computer vision, one can extract more information about traffic “dynamics” than by using traditional inductive loop detectors. Collecting arrival times of multiple vehicles after the first arrival at the stop-bar detector might be challenging when using inductive loop detectors (since after the first arrival, detector status is always occupied). However, emerging video detection systems allow tracking of each vehicle’s entrance time in the detection zone, departure time from the detection zone, and the type of vehicle. This information can be used to estimate vehicular arrival and departure times, which then can be fed into machine learning algorithms to estimate arrivals on green (AOG). However, such research ideas have not been documented so far. Thus, this paper presents an estimation model for AOG, which was developed using multigene genetic programming. A robust experimental dataset was collected from a highly calibrated and validated microsimulation model of an 11-intersection corridor in Chattanooga, TN. The results of the model’s performance analysis showed the high accuracy of the training-, testing-, and validation datasets. The practical benefit of this model is that it can be applied to estimate arrival types at intersections where only stop-bar video detection exists.

Engineering↗
DOE OSTI2020

Methodology of Low Inductance Busbar Design for Three-Level Converters

Three-level (3L) converters are more susceptible to parasitics compared with two-level converters because of their complicated structure with multiple switching loops. In this article, the methodology of busbar layout design for 3L converters based on the magnetic cancellation effect is presented. The methodology can fit for 3L converters with symmetric and asymmetric configurations. A detailed design example is provided for a high-power 3L-active neutral point clamped (ANPC) converter, which includes the module selection, busbar layout, and dc-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. Furthermore, the results match with each other, and the inductances of short and long loops are 6.5 and 17.5 nH, respectively, which are significantly lower than the busbars of NPC-type converters in other references.

42 ENGINEERING↗
DOE OSTI2023

PCB-on-DBC GaN Power Module Design with High-Density Integration and Double-Sided Cooling

Lateral gallium nitride (GaN) high-electron-mobility transistors (HEMTs) present better electrical characteristics compared to silicon or silicon carbide devices such as high switching speed and low gate charge, but also present additional challenges on the module design. Here, this paper discusses a high-density GaN power module with double-sided cooling, low inductance, on-package decoupling capacitors, and integrated gate drivers. The GaN dies as well as the gate drive are sandwiched between the printed circuit board (PCB) and direct bonded copper (DBC) substrate to achieve compact loop and double-sided cooling effect. Design considerations and thermal performance are analyzed. A module assembly procedure is presented utilizing the layer-by-layer attachment process. Finally, a 2.7 cm x 1.8 cm half-bridge GaN power module is fabricated and tested, achieving a low power-loop inductance of 1.03 nH, and the overshoot voltage of the switching waveform is less than 5% under a 400-V/25-A double-pulse test. The thermal resistance is 0.32 K/W, verified by simulation and experimental results. The design and assembly process can be generalized and applied to high power applications to achieve high power density and high performance.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2023

Cycle-by-cycle Delay Estimation at Signalized Intersections by using Machine Learning and Simulated Video Detection Data

Accurate estimation of delay is crucial for efficient traffic signal operations. Estimation of delay in the real-time manner using traditional loop detectors requires advanced detectors (in addition to stop-bar detection). In cases when this detection layout is not in place, delay estimates are approximated with a lower accuracy. Video detection is one of the most frequently deployed detection systems at signalized intersections in recent years. In most cases video detection operates in the same way as traditional inductive loops. However, when coupled with computer vision algorithms, video detection systems could be used to retrieve additional information (e.g., vehicular arrivals and departures) that cannot be taken out from the conventional systems (e.g., long stop-bar loop detectors). Although present for several decades, video detection data were not frequently examined for delay estimation purposes. In this study, we proposed a novel delay estimation model which can be developed with only data from stop-bar video detectors. Relevant data were collected from a simulation model of 11 signalized intersections at downtown Chattanooga, TN and processed to create needed inputs for model development. With the use of multigene genetic programming the authors developed a delay model that outperforms accuracy of multi regression model. Furthermore, authors evaluated the developed model by comparison with the other benchmark delay models, such as HCM and approach delay model. It was found that the developed MGGP delay model outperforms benchmark models for a wide range of traffic and signal operation conditions.

Erdagi, Ismet Goksad↗
DOE OSTI2023

A superconducting nanowire binary shift register

We present a design for a superconducting nanowire binary shift register, which stores digital states in the form of circulating supercurrents in high-kinetic-inductance loops. Adjacent superconducting loops are connected with nanocryotrons, three-terminal electrothermal switches, and fed with an alternating two-phase clock to synchronously transfer the digital state between the loops. A two-loop serial-input shift register was fabricated with thin-film NbN and a bit error rate of less than 10 –4 was achieved, when operated at a maximum clock frequency of 83 MHz and in an out-of-plane magnetic field of up to 6 mT. A shift register based on this technology offers an integrated solution for low-power readout of superconducting nanowire single photon detector arrays and is capable of interfacing directly with room-temperature electronics and operating unshielded in high magnetic field environments.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2022

Comparative Investigation of Current-Source Inverters using SiC Discrete Devices and Power Modules

The purpose of this paper is to investigate the impact of the SiC device packages on the commutation performance characteristics of current-source inverters (CSIs). The parasitic components in the CSI current commutation loop between the two-phase legs and output capacitors have a significant impact on the high-frequency performance of the SiC devices. To meet the elevated current requirements of high-power CSIs, it is often necessary to connect multiple discrete devices in parallel which increases the current commutation loop length. The selection of compact high-power SiC MOSFET and Schottky diode modules instead of discrete devices can be highly desirable to reduce the loop inductance and improve the system performance and power density. Two CSI benchtop prototype units, one with SiC discrete devices and the other with power modules, have been designed and tested, and the performances of the two CSIs are compared. The CSI with SiC power modules significantly reduces the inverter volume and lowers the parasitic inductance by 60% and the voltage ripple amplitude by 20% compared to the CSI unit with discrete devices.

42 ENGINEERING↗
DOE OSTI2025

Organic Direct-Bonded-Copper-Based Rapid Prototyping for Silicon Carbide Power Module Packaging

Silicon carbide (SiC) power devices are playing ever- growing roles in high-power-density power electronics converters by offering benefits such as high voltage rating, fast transients, and high thermal performance. Organic direct-bonded copper (ODBC)-based packaging, due to its ductility and ease of han- dling, allows the possibility of a more flexible layout design that may better tap the potential of SiC benefits. In this work, an ODBC-based prototyping routine is developed that accelerates the iterations of packaging layout design with low cost. The properties of ODBC and its handling are briefly introduced, and tools and fabrication steps are explained. Following this routine, a 1.2-kV SiC half-bridge power module is designed and fabricated with the focus on sub-nanohenry ultra-low loop inductance. Simulation and experimental validation are also conducted.

25 ENERGY STORAGE↗
DOE OSTI2020

Integrating Overhead Camera Imagery with Reinforcement Learning to Improve Fuel Economy Through Adaptive Traffic Control

Overhead cameras have been deployed for some time as a sensor for traffic control, with many advantages over conventional inductive loop sensors in terms of robustness, ease of installation, and simplicity with respect to maintenance. We explore the utility of such imagery (in particular, fisheye lens cameras) for intelligent traffic control in real-time using reinforcement learning, with a goal of improving fuel economy for the overall intersection and grid of intersections. We summarize our initial work in data collection and approach to ascertain the ability to visually sense vehicular fuel consumption using real-world data. We then describe our deep reinforcement learning topology to test adaptive control informed by the camera capabilities. Next, we tested the proof-of-concept through a variety of simulation scenarios using the Simulation of Urban Mobility (SUMO) traffic simulator, which included different estimates on vehicle classifications, different traffic distributions, and different traffic densities. Six different control policies were tested ranging from simple timing, to heuristic visual-based methods, to actual policies learned via the reinforcement learning approach. Our results demonstrate the feasibility of the approach for controlling traffic lights for better fuel efficiency based on visual vehicle estimates from commercial, fisheye lens cameras.

Karnowski, Thomas↗
DOE OSTI2022

Power module with organic layers

A power module is provided with reduced power and gate loop inductance. The power module may be configured in a multi-layer manner with one or more organic substrates.

Gurpinar, Emre↗
DOE OSTI2022

Non-inductive plasma vertical position measurement for the 1056 s discharge on EAST

Vertical position stability plays a crucial role in maintaining safe and reliable plasma operation for long-pulse fusion devices. In general, the vertical position is measured by using inductive magnetic coils installed inside the vacuum vessel; however, the integration drift effects are inherent for steady-state or long-pulse plasma operation. Further, developing a non-magnetic approach provides a fusion reactor-relevant steady-state solution that avoids the negative impact of integration drift. In this paper, we compare the non-inductively determined vertical position achieved by line-integrated interferometer and polarimeter measurements to that employing an inductive flux loop for a 1056 s discharge recently achieved on EAST (Experimental Advanced Superconducting Tokamak). Experimental results show that the non-inductive measurement is more robust than flux loops after 300 s if the integrator is not reset to suppress integrator drift. Real-time vertical position control using the non-inductive system is proposed for the next EAST experimental campaign.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2026

Multi-machine validation of plasma initiation modelling and prospects for future devices: Predicting plasma initiation using only hardware design and control room input data

This paper reports on the generic prediction capability of full electromagnetic plasma initiation modelling with DYON, which was carried out for the first time in fusion research by the joint modelling of the International Tokamak Physics Activity—Integrating Operation Scenario group. The following devices were included in the experiment database: VEST (spherical torus, copper coils, Stainless steel wall, R/a = 0.3 m/0.2 m, V v = 3.7 m 3 ), MAST-U (spherical torus, copper coils, C wall, R/a = 0.7 m/0.5 m, V v = 55 m 3 ), EAST (conventional tokamak, superconducting coils, metallic wall, R/a = 1.85 m/0.5 m, V v = 38 m 3 ), DIII-D (conventional tokamak, copper coils, C wall, R/a = 1.67 m/0.65 m, V v = 35 m 3 ), and KSTAR (conventional tokamak, superconducting coils, C wall, R/a = 1.8 m/0.5 m, V v = 55 m 3 ). Despite the different hardware features of the devices, the required operating spaces of the loop voltage induction and prefill gas pressure for inductive plasma initiation in each device were successfully reproduced by the predictive simulations with DYON using only the individual hardware design and the control room input data for each discharge. This successful validation across multiple machines demonstrates that the full electromagnetic DYON modelling can capture the essential physics of inductive plasma initiation. The simulation settings commonly employed for all modelling and the modifications necessary to account for the discrepancies between individual devices are reported. Predictions for ITER based on the multi-machine validation indicate that a wide range of prefill gas pressures exists for the Townsend breakdown and the plasma burn-through (0.01–1.5 mPa).

DYON↗