Search NASA⌕ Search

SEARCH · Search NASA

Results for “inverter synchronization”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1976

Static inverter with synchronous output waveform synthesized by time-optimal-response feedback

Time-optimal-response 'bang-bang' or 'bang-hang' technique, using four feedback control loops, synthesizes static-inverter sinusoidal output waveform by self-oscillatory but yet synchronous pulse-frequency-modulation (SPFM). A single modular power stage per phase of ac output entails the minimum of circuit complexity while providing by feedback synthesis individual phase voltage regulation, phase position control and inherent compensation simultaneously for line and load disturbances. Clipped sinewave performance is described under off-limit load or input voltage conditions. Also, approaches to high power levels, 3-phase arraying and parallel modular connection are given.

Kernick, A.↗
NASA NTRS1986

Resonant AC power system proof-of-concept test program

Proof-of-concept testing was performed on a 20-kHz, resonant power system breadboard from 1981 through 1985. The testing began with the evaluation of a single, 1.0-kW resonant inverter and progressed to the testing of breadboard systems with higher power levels and more capability. The final breadboard configuration tested was a 25.0-kW breadboard with six inverters providing power to three user-interface modules over a 50-meter, 20-kHz bus. The breadboard demonstrated the ability to synchronize multiple resonant inverters to power a common bus. Single-phase and three-phase 20-kHz power distribution was demonstrated. Simple conversion of 20-kHz to dc and variable-frequency ac was demonstrated as was bidirectional power flow between 20-kHz and dc. Steady state measurements of efficiency, power-factor tolerance, and conducted emissions and conducted susceptibility were made. In addition, transient responses were recorded for such conditions as start up, shut down, load changes. The results showed the 20-kHz resonant system to be a desirable technology for a spacecraft power management and distribution system with multiple users and a utility-type bus.

Wappes, Loran J.↗
NASA NTRS1980

Alternate symbol inversion for improved symbol synchronization in convolutionally coded systems

Inverting alternate symbols of the encoder output of a convolutionally coded system provides sufficient density of symbol transitions to guarantee adequate symbol synchronizer performance, a guarantee otherwise lacking. Although alternate symbol inversion may increase or decrease the average transition density, depending on the data source model, it produces a maximum number of contiguous symbols without transition for a particular class of convolutional codes, independent of the data source model. Further, this maximum is sufficiently small to guarantee acceptable symbol synchronizer performance for typical applications. Subsequent inversion of alternate detected symbols permits proper decoding.

Simon, M. K.↗
NASA NTRS1976

Single phase inverter for a three phase power generation and distribution system

A breadboard design of a single-phase inverter with sinusoidal output voltage for a three-phase power generation and distribution system was developed. The three-phase system consists of three single-phase inverters, whose output voltages are connected in a delta configuration. Upon failure of one inverter the two remaining inverters will continue to deliver three-phase power. Parallel redundancy as offered by two three-phase inverters is substituted by one three-phase inverter assembly with high savings in volume, weight, components count and complexity, and a considerable increase in reliability. The following requirements must be met: (1) Each single-phase, current-fed inverter must be capable of being synchronized to a three-phase reference system such that its output voltage remains phaselocked to its respective reference voltage. (2) Each single-phase, current-fed inverter must be capable of accepting leading and lagging power factors over a range from -0.7 through 1 to +0.7.

Lindena, S. J.↗
NASA NTRS1987

CMOS Clock Synchronizer

Circuit synchronizes clock and gate signals within one-quarter of clock cycle. Clock synchronizer with one-quarter-cycle skew constructed from three flip-flops, three NAND gates, and inverter. In addition gate signal to which clock synchronized, circuit requires square-wave input at twice desired clock frequency.

Kepp, R. B.↗
NASA NTRS2012

Fifteen Years of Operation at NASA's National Transonic Facility with the World's Largest Adjustable Speed Drive

In September 1995, a project was initiated to replace the existing drive line at NASA's most unique transonic wind tunnel, the National Transonic Facility (NTF), with a single 101 MW synchronous motor driven by a Load Commutated Inverter (LCI). This Adjustable Speed Drive (ASD) system also included a custom four-winding transformer, harmonic filter, exciter, switch gear, control system, and feeder cable. The complete system requirements and design details have previously been presented and published [1], as well as the commissioning and acceptance test results [2]. The NTF was returned to service in December 1997 with the new drive system powering the fan. Today, this installation still represents the world s largest horizontal single motor/drive combination. This paper describes some significant events that occurred with the drive system during the first 15 years of service. These noteworthy issues are analyzed and root causes presented. Improvements that have substantially increased the long term viability of the system are given.

Sydnor, George H.↗
NASA NTRS2017

A Study of the Degradation of Electronic Speed Controllers for Brushless DC Motors

Brushless DC motors are frequently used in electric aircraft and other direct drive applications. As these motors are notactually direct current machines but synchronous alternating current machines; they are electronically commutated by a power inverter. The power inverter for brushless DC motors typically used in small scale UAVs is a semiconductor base delectronic commutator that is external to the motor and is referred to as an electronic speed control (ESC). This paper examines the performance changes of a UAV electric propulsion system resulting from ESC degradation. ESC performance is evaluated in simulation and on a new developed test bed featuring propulsion components from a reference UAV. An increase in the rise fall times of the switched voltages is expected to cause timing issues at high motor speeds. This study paves the way for further development of diagnostic and prognostic methods for inverter circuits which are part of the overall electric UAV system.

Gorospe, George E., Jr.↗
NASA NTRS2006

General Solution for Theoretical Packet Data Loss Rate

Communications systems which transfer blocks ("frames") of data must use a marker ("frame synchronization pattern") for identifying where a block begins. A technique ("frame synchronization strategy") is used to locate the start of each frame and maintain synchronization as additional blocks are processed. A device which strips out the frame synchronization pattern [FSP] and provides an "end of frame" pulse is called a frame synchronizer. As clock and data errors are introduced into the system, the start-of-block marker becomes displaced and/or corrupted. The capability of the frame synchronizer to stay locked to the pattern under these conditions is a figure of merit for the frame synchronization strategy. It is important to select a strategy which will stay locked nearly all the time at bit error rates where the data is usable. ("Bit error rate" [BER] is the fraction of binary bits which are inverted by passage through a communication system.) The fraction of frames that are discarded because the frame synchronizer is not locked is called "Percent Data Loss" or "Packet Data Loss rate" [PDL]. A general approach for accurately predicting PDL given BER was developed in Theoretical Percent Data Loss Calculation and Measurement Accuracy, T. P. Kelly, LESC-30554, December 1992. Kelly gave a solution in terms of matrix equations, and only addressed "level" channel encoding. This paper goes on to give a closed-form polynomial solution for the most common class of frame synchronizer strategies, and will also address "mark" and "space" (differential) channel encoding, and burst error environments. The paper is divided into four sections and follows a logically ordered presentation, with results developed before they are evaluated. However, most readers will derive the greatest benefit from this paper by treating the results as reference material. The result developed for differential encoding can be extended to other applications (like block codes) where the probability is needed that a block contains only a certain number of errors.

Lansdowne, Chatwin↗
NASA NTRS1996

Phase-shifting human circadian rhythms: influence of sleep timing, social contact and light exposure

1. Both the timing of behavioural events (activity, sleep and social interactions) and the environmental light-dark cycle have been reported to contribute to entrainment of human circadian rhythms to the 24 h day. Yet, the relative contribution of those putative behavioural synchronizers to that of light exposure remains unclear. 2. To investigate this, we inverted the schedule of rest, sedentary activity and social contact of thirty-two young men either with or without exposure to bright light. 3. On this inverted schedule, the endogenous component of the core temperature rhythm of subjects who were exposed to bright light showed a significant phase shift, demonstrating that they were adapting to the new schedule. In contrast, the core temperature rhythm of subjects who were not exposed to bright light moved on average 0.2 h later per day and after 10 days had not significantly adapted to the new schedule. 4. The direction of phase shift in the groups exposed to bright light was dependent on the time of bright light exposure, while control subjects drifted to a later hour regardless of the timing of their schedule of sleep timing, social contact and meals. 5. These results support the concept that the light-dark cycle is the most important synchronizer of the human circadian system. They suggest that inversion of the sleep-wake, rest-activity and social contact cycles provides relatively minimal drive for resetting the human circadian pacemaker. 6. These data indicate that interventions designed to phase shift human circadian rhythms for adjustment to time zone changes or altered work schedules should focus on properly timed light exposure.

Non-NASA Center↗
NASA NTRS1980

Power processing and control requirements of dispersed solar thermal electric generation systems

Power Processing and Control requirements of Dispersed Receiver Solar Thermal Electric Generation Systems are presented. Kinematic Stirling Engines, Brayton Engines and Rankine Engines are considered as prime movers. Various types of generators are considered for ac and dc link generations. It is found that ac-ac Power Conversion is not suitable for implementation at this time. It is also found that ac-dc-ac Power Conversion with a large central inverter is more efficient than ac-dc-ac Power Conversion using small dispersed inverters. Ac-link solar thermal electric plants face potential stability and synchronization problems. Research and development efforts are needed in improving component performance characteristics and generation efficiency to make Solar Thermal Electric Generation economically attractive.

Das, R. L.↗
NASA NTRS1983

Effects of voltage control in utility interactive dispersed storage and generation systems

When a small generator is connected to the distribution system, the voltage at the point of interconnection is determined largely by the system and not the generator. The effect on the generator, on the load voltage and on the distribution system of a number of different voltage control strategies in the generator is examined. Synchronous generators with three kinds of exciter control are considered, as well as induction generators and dc/ac inverters, with and without capacitor compensation. The effect of varying input power during operation (which may be experienced by generators based on renewable resources) is explored, as well as the effect of connecting and disconnecting the generator at ten percent of its rated power. Operation with a constant slightly lagging factor is shown to have some advantages.

Kirkham, H.↗
NASA NTRS1986

Unbalanced-to-Balanced Video Interface

Equal but opposite video waveforms generated. Unbalanced input line terminated in 75-ohm resistor, R1. Capacitor C1 blocks dc component of input so only time-varying component fed to Q1 and inverted in polarity. Circuit intended for use with input television signal having polarity, amplitude, and dc bias such that tips of synchronizing pulses lie at zero volts while reference white level is specified positive dc level (typically about 1 volt).

Richardson, J. E.↗
NASA NTRS2023

Analytical Design and Performance Estimation Methods for Aircraft Permanent Magnet Synchronous Machines

The design of an electric motor drivetrain is a complex multiphysics problem. Low fidelity motor drivetrain sizing can be a key tool in the design cycle of an electric motor drivetrain and for system level studies of aircraft configurations. However, low fidelity sizing can lead to misleading results if all the physics involved in a motor design are not properly accounted for. This paper provides details on modeling approaches for initial design and sizing of permanent magnet synchronous electric machines. The goal of this paper is to provide the reader an understanding of the key principles of motor design and some modeling approaches to perform initial sizing of an electric motor and its inverter.

Thomas F. Tallerico↗
NASA NTRS1972

A north-south stationkeeping ion thruster system for ATS-F.

An ion thruster system is being developed for the ATS-F satellite to demonstrate the application of ion thruster technology to the synchronous satellite north-south stationkeeping mission. The cesium bombardment ion thruster develops one millipound thrust at 2600 seconds specific impulse and provides thrust vectoring by accelerator electrode displacement. The propellant system is sized for two years operation at 25 percent duty cycle. Power conditioning circuitry is based on transistor inverters switching at 10 kHz. Thirteen command channels allow flexibility in operation; 12 telemetry channels provide information on system performance. Input power is less than 150 watts.

Worlock, R.↗
NASA NTRS1991

Phase ambiguity resolution for offset QPSK modulation systems

A demodulator for Offset Quaternary Phase Shift Keyed (OQPSK) signals modulated with two words resolves eight possible combinations of phase ambiguity which may produce data error by first processing received I(sub R) and Q(sub R) data in an integrated carrier loop/symbol synchronizer using a digital Costas loop with matched filters for correcting four of eight possible phase lock errors, and then the remaining four using a phase ambiguity resolver which detects the words to not only reverse the received I(sub R) and Q(sub R) data channels, but to also invert (complement) the I(sub R) and/or Q(sub R) data, or to at least complement the I(sub R) and Q(sub R) data for systems using nontransparent codes that do not have rotation direction ambiguity.

Nguyen, Tien M.↗
NASA NTRS2010

A 311-GHz Fundamental Oscillator Using InP HBT Technology

This oscillator uses a single-emitter 0.3- m InP heterojunction bipolar transistor (HBT) device with maximum frequency of oscillation (fmax) greater than 500 GHz. Due to high conductor and substrate losses at submillimeterwave frequencies, a primary challenge is to efficiently use the intrinsic device gain. This was done by using a suitable transmission-line media and circuit topology. The passive components of the oscillator are realized in a twometal process with benzocyclobutene (BCB) used as the primary transmission line dielectric. The circuit was designed using microstrip transmission lines. The oscillator is implemented in a common-base topology due to its inherent instability, and the design includes an on-chip resonator, outputmatching circuitry, and an injection-locking port, the port being used to demonstrate the injection-locking prin ciple. A free-running frequency of 311.6 GHz has been measured by down-converting the signal. Ad di tionally, injection locking has been successfully demonstrated with up to 17.8 dB of injection-locking gain. The injection-locking reference signal is generated using a 2 20 GHz frequency synthesizer, followed by a doubler, active tripler, a W-band amplifier, and then a passive tripler. Therefore, the source frequency is multiplied 18 times to obtain a signal above 300 GHz that can be used to injection lock the oscillator. Measurement shows that injection locking has improved the phase noise of the oscillator and can be also used for synchronizing a series of oscillators. A signal conductor is implemented near the BCP -InP interface and the topside of the BCB layer is fully metallized as a signal ground. Because the fields are primarily constrained in the lower permittivity BCB region, this type of transmission line is referred to as an inverted microstrip. In addition, both common-emitter and commonbase circuits were investigated to determine optimum topology for oscillator design. The common -base topology required smaller amount of feedback than the common-emitter design, therefore preserving device gain, and was chosen for the oscillator design. The submillimeter-wave region offers several advantages for sensors and communication systems, such as high resolution and all-weather imaging due to the short-wavelength, and improved communication speeds by access to greater frequency bandwidth. This oscillator circuit is a prototype of the first HBT oscillator operating above 300 GHz. Additional development is necessary to increase the output power of the circuit for radar and imaging applications.

Gaier, Todd↗
NASA NTRS2004

Reduction of Phase Ambiguity in an Offset-QPSK Receiver

Proposed modifications of an offset-quadri-phase-shift keying (offset-QPSK) transmitter and receiver would reduce the amount of signal processing that must be done in the receiver to resolve the QPSK fourfold phase ambiguity. Resolution of the phase ambiguity is necessary in order to synchronize, with the received carrier signal, the signal generated by a local oscillator in a carrier-tracking loop in the receiver. Without resolution of the fourfold phase ambiguity, the loop could lock to any of four possible phase points, only one of which has the proper phase relationship with the carrier. The proposal applies, more specifically, to an offset-QPSK receiver that contains a carrier-tracking loop like that shown in Figure 1. This carrier-tracking loop does not resolve or reduce the phase ambiguity. A carrier-tracking loop of a different design optimized for the reception of offset QPSK could reduce the phase ambiguity from fourfold to twofold, but would be more complex. Alternatively, one could resolve the fourfold phase ambiguity by use of differential coding in the transmitter, at a cost of reduced power efficiency. The proposed modifications would make it possible to reduce the fourfold phase ambiguity to twofold, with no loss in power efficiency and only relatively simple additional signal-processing steps in the transmitter and receiver. The twofold phase ambiguity would then be resolved by use of a unique synchronization word, as is commonly done in binary phase-shift keying (BPSK). Although the mathematical and signal-processing principles underlying the modifications are too complex to explain in detail here, the modifications themselves would be relatively simple and are best described with the help of simple block diagrams (see Figure 2). In the transmitter, one would add a unit that would periodically invert bits going into the QPSK modulator; in the receiver, one would add a unit that would effect different but corresponding inversions of bits coming out of the QPSK demodulator. The net effect of all the inversions would be that depending on which lock point the carrier-tracking loop had selected, all the output bits would be either inverted or non-inverted together; hence, the ambiguity would be reduced from fourfold to twofold, as desired.

Berner, Jeff↗