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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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13 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

Reliability of PWB Microvias for High Density Package Assembly

High density PWB (printed wiring board) with microvia technology is required for implementation of high density and high I/O area array packages (AAP). COTS (commercial off-the-shelf) AAP packaging technologies in high reliability versions with 1.27 mm pitch are now being considered for use in a number of NASA systems including Space Shuttle and Mars Rovers. NASA functional system designs are requiring more and more dense AAP packages and board space, which makes board microvia technology very attractive for effectively routing a large number of package inputs/outputs. However, the reliability of the fine feature microvias including via in pads is unknown for space applications. Understanding process and QA (quality assurance) indicators for reliability are important for low risk insertion of these newly available packages and PWBs. This paper presents literature search as well as test results for a high density board subjected to various thermal cycle and reflow profiles representative of tin-lead and lead-free solder reflow. Microvias sizes ranged from two to six mil with and without filling. Daisy chain microvias monitored during the test and PWBs were cross-sectioned to determine failure and locations. Optical and SEM photographs as well as resistance changes during cycling and Tg/Td (glass transition/decomposition temperature) characterisations are presented.

fill via↗
NASA NTRS1998

Chip Scale Package Implementation Challenges

The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. In the process of building the Consortium CSP test vehicles, many challenges were identified regarding various aspects of technology implementation. This paper will present our experience in the areas of technology implementation challenges, including design and building both standard and microvia boards, and assembly of two types of test vehicles. We also discuss the most current package isothermal aging to 2,000 hours at 100 C and 125 C and thermal cycling test results to 1,700 cycles in the range of -30 to 100 C.

Ghaffarian, Reza↗
NASA NTRS2000

CSP Manufacturing Challenges and Assembly Reliability

Although the expression of CSP is widely used by industry from suppliers to users, its implied definition had evolved as the technology has matured. There are "expert definition"- package that is up to 1.5 time die- or "interim definition". CSPs are miniature new packages that industry is starting to implement and there are many unresolved technical issues associated with their implementation. For example, in early 1997, packages with 1 mm pitch and lower were the dominant CSPs, whereas in early 1998 packages with 0.8 mm and lower became the norm for CSPs. Other changes included the use of flip chip die rather than wire bond in CSP. Nonetheless the emerging CSPs are competing with bare die assemblies and are becoming the package of choice for size reduction applications. These packages provide the benefits of small size and performance of the bare die or flip chip, with the advantage of standard die packages. The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. This talk will cover specifically the experience of our consortium on technology implementation challenges, including design and build of both standard and microvia boards, assembly of two types of test vehicles, and the most current environmental thermal cycling test results.

Ghaffarian, Reza↗
NASA NTRS2001

Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology for RF/Microwave Applications

In this paper, novel low loss, wide-band coplanar stripline technology for radio frequency (RF)/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth, and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semi-conductor devices and microelectromechanical systems (MEMS).

Simons, Rainee N.↗
NASA NTRS2001

Novel Vertical Interconnects With 180 Degree Phase Shift for Amplifiers, Filters, and Integrated Antennas

In this paper, novel low loss, wide-band coplanar stripline technology for RF/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semiconductor devices and microelectromechanical systems (MEMS).

Goverdhanam, Kavita↗
NASA NTRS2007

Materials Development for Auxiliary Components for Large Compact Mo/Au TES Arrays

We describe our current fabrication process for arrays of superconducting transition edge sensor microcalorimeters, which incorporates superconducting Mo/Au bilayers and micromachined silicon structures. We focus on materials and integration methods for array heatsinking with our bilayer and micromachining processes. The thin superconducting molybdenum bottom layer strongly influences the superconducting behavior and overall film characteristics of our molybdenum/gold transition-edge sensors (TES). Concurrent with our successful TES microcalorimeter array development, we have started to investigate the thin film properties of molybdenum monolayers within a given phase space of several important process parameters. The monolayers are sputtered or electron-beam deposited exclusively on LPCVD silicon nitride coated silicon wafers. In our current bilayer process, molybdenum is electron-beam deposited at high wafer temperatures in excess of 500 degrees C. Identifying process parameters that yield high quality bilayers at a significantly lower temperature will increase options for incorporating process-sensitive auxiliary array components (AAC) such as array heat sinking and electrical interconnects into our overall device process. We are currently developing two competing technical approaches for heat sinking large compact TES microcalorimeter arrays. Our efforts to improve array heat sinking and mitigate thermal cross-talk between pixels include copper backside deposition on completed device chips and copper-filled micro-trenches surface-machined into wafers. In addition, we fabricated prototypes of copper through-wafer microvias as a potential way to read out the arrays. We present an overview on the results of our molybdenum monolayer study and its implications concerning our device fabrication. We discuss the design, fabrication process, and recent test results of our AAC development.

Finkbeiner, F. m.↗
NASA NTRS2014

Reliability of CGA/LGA/HDI Package Board/Assembly (Final Report)

Package manufacturers are now offering commercial-off-the-shelf column grid array (COTS CGA) packaging technologies in high-reliability versions. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronics packages. The previous reports, released in January of 2012 and January of 2013, presented package test data, assembly information, and reliability evaluation by thermal cycling for CGA packages with 1752, 1517, 1509, and 1272 inputs/outputs (I/Os) and 1-mm pitch. It presented the thermal cycling (-55C either 100C or 125C) test results for up to 200 cycles. This report presents up to 500 thermal cycles with quality assurance and failure analysis evaluation represented by optical photomicrographs, 2D real time X-ray images, dye-and-pry photomicrographs, and optical/scanning electron Microscopy (SEM) cross-sectional images. The report also presents assembly challenge using reflowing by either vapor phase or rework station of CGA and land grid array (LGA) versions of three high I/O packages both ceramic and plastic configuration. A new test vehicle was designed having high density interconnect (HDI) printed circuit board (PCB) with microvia-in-pad to accommodate both LGA packages as well as a large number of fine pitch ball grid arrays (BGAs). The LGAs either were assembled onto HDI PCB as an LGA or were solder paste print and reflow first to form solder dome on pads before assembly. Both plastic BGAs with 1156 I/O and ceramic LGAs were assembled. It also presented the X-ray inspection results as well as failures due to 200 thermal cycles. Lessons learned on assembly of ceramic LGAs are also presented.

Ghaffaroam. Reza↗
NASA NTRS1999

Manufacturing Robustness of CSP in SMT Line

In this paper, the assembly process flow, solder paste for different stencil design, manufacturing defects, X-ray inspection results, and ultrasonic characterizations are reported.

electronic assembly SMT CSP fine pitch microvia te↗