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Results for “minimized decoupling capacitor”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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4 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Highly Reliable Multi-Port Smart Inverter Modules for PV-Based Energy Systems

Generally, large electrolytic capacitors (E-caps) are required to decouple the double-line frequency power fluctuation inherent in all single-phase dc-ac or ac-dc converters. These E-caps pose the weak link in the photovoltaic (PV) inverter because they have poor reliability as a result of short life expectancy and higher equivalent series resistance (ESR) which leads to lower system efficiency. In this paper, multiport smart dual-inverter modules are proposed for residential PV inverter systems with balanced outputs to eliminate the requirement of large decoupling capacitors, thus leading to more reliable and highly efficient inverter modules. The balanced dual outputs are controlled in phase quadrature such that the double frequency current is completely eliminated. One phase supports the standalone residential loads, and the other phase interfaces with the grid, which is synchronized to the utility grid. Also, the proposed modular configuration is scalable to accommodate higher power rating by stacking and paralleling multiple modules. Simulation results for the dual-inverter modules rated for 1 kW each are presented to validate the proposed concept. Experimental results from a controller hardware-in-the-loop (CHIL) platform also verify its feasibility.

14 SOLAR ENERGY↗
DOE OSTI2020

Estimation, Minimization, and Validation of Commutation Loop Inductance for a 135-kW SiC EV Traction Inverter

With growing interests in low inductance SiC based power module packaging, it is vital to focus on system level design aspects to facilitate easy integration of the modules and reap system level benefits. To effectively utilize the low inductance modules, busbar and interconnects should also be designed with low stray inductances. A wholistic investigation of the flux path and flux cancellations in the module-busbar assembly which as differentially coupled series inductors is thus mandatory for a system level design. This work presents a busbar design which can be adopted to effectively integrate the CREE’s low inductance 1.2 kV/1.7 kV SiC power modules. The paper also proposes a novel measurement technique to measure the inductance of the modulebusbar assembly as a whole rather than deducing it from individual components. The inductance of the overall commutation loop of the inverter which encompasses the SiC power module, interconnects and PCB busbar have been estimated using finite element analysis (FEA). Furthermore, insights gained from FEA provided the guidelines to decide on the placement of the decoupling capacitors in the busbar to minimize the overall commutation loop inductance from 12.8 nH to 7.4 nH which resulted in significant reduction in the device voltage overshoot. The simulation results have been validated through measurements using an impedance analyzer with less than 5% difference between extracted loop inductance from FEA and measurements. The bus bar design study and the measurement technique discussed in this paper, can be easily extended to other power module packages. Finally, the 135 kW inverter has been compared to a similar highpower inverter utilizing a laminated busbar to highlight the performance of the former.

42 ENGINEERING↗
DOE OSTI2020

Busbar Design and Optimization for Voltage Overshoot Mitigation of a Silicon Carbide High-Power Three-Phase T-Type Inverter

The silicon carbide (SiC) devices have faster switching speed than that of the conventional silicon (Si) devices, which however may cause excessive device voltage overshoot. Larger gate resistance can help to restrain the overshoot, it however slows down the switching speed and increases switching losses. There are other methods that can mitigate the voltage overshoot, e.g., using low-inductance busbars, adding snubber circuits, etc. In this article, the busbar design for a 250-kW SiC three-level T-type inverter is investigated. The current commutation loops (CCLs) are first analyzed using a single-phase equivalent circuit. Then the detailed busbar design methods, especially a 3-D busbar design concept, are proposed to select the optimal stacking order for the multilayer laminated busbar and to address constraints posed by the physical terminal arrangements of SiC modules and dc-link capacitors. The stray inductance in each CCL is extracted via a finite element analysis and validated on the actual inverter busbar prototypes using an impedance analyzer. To further minimize the busbar stray inductance, a hybrid busbar structure with printed circuit board based buffer circuit using high-frequency decoupling capacitors is designed and evaluated in this article. Lastly, the effectiveness of the designed busbars as well as the buffer circuit are validated using experimental studies.

42 ENGINEERING↗
DOE OSTI2024

Stacked-Die SiC Half-Bridge Module with Minimum Loop Inductance

Minimizing parasitic inductance of power modules is needed to advance their electrical performance. Innovation in the past decade has driven down the inductance of SiC half-bridge power modules to around 1–2 nH by using multilayer, embedded, and hybrid structures. Further reduction becomes difficult, mainly limited by the excessive interconnects required for the planar placement of vertical conducting chips. To address this, a vertically stacked-die approach is proposed in this paper, taking advantage of the vertical conducting nature of the SiC chips. With ceramic decoupling capacitors integrated, 0.48 nH overall loop inductance is achieved and validated by experimental measurement. This paper also discusses potential approaches to further reduce the inductance.

Ribeiro, Pedro↗