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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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15 records

All sources NASA NTRS DOE OSTI

DOE OSTI2020

Fault-tolerant controller for modular multi-level converters

Various examples are provided related to fault-tolerant controller architectures for multi-level converters. In one example, a multi-level converter includes an array of power modules. The power modules can include a controller communicatively coupled to controllers of adjacent power modules in the array of power modules. Circuitry of the controllers can receive operational data from the adjacent power modules; identify a fault condition in an adjacent power module using the operational data; and initiate reconfiguration of the array of power modules in response to an indication of the fault condition, where the reconfiguration bypasses the adjacent power module. In another example, a method includes identifying a fault condition in an adjacent power module in an array of power modules based upon operational data from one or more adjacent power modules of the array; and initiating reconfiguration of the array of power modules in response to an indication of the fault condition.

42 ENGINEERING↗

DOE OSTI2020

Capacitor Voltage Ripple Estimation and Optimal Sizing of Modular Multi-Level Converters for Variable-Speed Drives

This article deals with the sizing of submodule capacitors for modular multilevel converters (MMCs) used for variable speed drives for medium voltage and high voltage electric machines. Variable speed drives are required to run over a wide frequency range from zero to a few hundred Hz or even over 1 kHz. Under low frequency operation (<30 Hz), a large current ripple flowing through the MMC submodule capacitors will cause significant capacitor voltage fluctuation. This article proposes an optimal submodule capacitor selection method based on the common-mode voltage injection. The proposed sizing model includes two functions: 1) accurately estimating the capacitor voltage ripple based on the drive system parameters; and 2) identifying the minimum capacitance of the submodule capacitors based on the allowed maximum capacitor voltage fluctuations. Simulation and experimental results show that the error between the actual and estimated values of the voltage fluctuation is within 3% using the proposed model.

42 ENGINEERING↗

DOE OSTI2022

Decentralized Interleaving of Cascaded H-Bridge Multi-Level Converters

This document proposes a simple method to decentralize the interleaving for cascaded H bridge (CHB) converters. In the proposed approach, a single signal sent from the Central controller (CC) to Local Controllers (LC) contains information about the desired pulse width and is synchronized with respect to other LC. While centralized controllers need individual signals for each of the CHB modules, the proposed method requires a single signal per phase which decreases the number of PWM channels needed. A detailed explanation of the proposed method is presented. Experimental results are presented that show the interleaving of two CHB modules for an example DC to AC application.

Montes, Oscar Andres↗

DOE OSTI2021

Real-time Implementation of a Dual-Active-Bridge Based Multi-Level Photovoltaic Converter

Silicon-carbide based, multi-level converters with dual-active-bridge (DAB) are getting attention for medium voltage, direct grid-connected, utility-scale photovoltaic (PV) applications due to their higher efficiency and power density. To de-risk complex control development for these high-voltage and high-power inverters, hardware-in-the-loop techniques are often required. Due to the high switching frequency and the large number of power electronic switches, off-the-shelf, real-time simulation tools are not yet fully developed for this application, even with FPGA-based simulators. To address this, a new co-simulation approach in FPGA is presented that utilizes Time-Stamped Bridge (TSB) for the higher frequency converters along with detailed fixed conductance based discrete device simulation of the rest of the circuit. A complex DAB-based PV converter with maximum switching frequency of 50 kHz is successfully simulated in real-time in the FPGA and the results are compared with offline simulation results. A controller hardware-in-the-loop (CHIL) platform is developed to demonstrate real-time, closed-loop test results for this DAB-based PV converter.

Dong, Zerui↗

DOE OSTI2021

Fault location in High Voltage Multi-terminal dc Networks Using Ensemble Learning

Precise location of faults for large distance power transmission networks is essential for faster repair and restoration process. High Voltage direct current (HVdc) networks using modular multi-level converter (MMC) technology has found its prominence for interconnected multi-terminal networks. This allows for large distance bulk power transmission at lower costs. However, they cope with the challenge of dc faults. Fast and efficient methods to isolate the network under dc faults have been widely studied and investigated. After successful isolation, it is essential to precisely locate the fault. The post-fault voltage and current signatures are a function of multiple factors and thus accurately locating faults on a multi-terminal network is challenging. In this paper, we discuss a novel data-driven ensemble learning based approach for accurate fault location. Here we utilize the eXtreme Gradient Boosting (XGB) method for accurate fault location. The sensitivity of the proposed algorithm to measurement noise, fault location, resistance and current limiting inductance are performed on a radial three-terminal MTdc network designed in Power System Computer Aided Design (PSCAD)/Electromagnetic Transients including dc (EMTdc).

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2021

The Impact of the Lightning Surge on SiC-based Medium-voltage Three-phase Four-wire Grid-connected Converters

The surge voltage induced by lightning will generate an inrush current in a grid-connected converter. It may not be large in Si-based converters because of the large grid side inductive filter. However, for SiC-based multi-level converters, the inrush current could be very large due to the small filter inductance, which is selected based on the current harmonic consideration. Most previous work focuses on system-level lightning protection while the converter-level impact, especially the internal components of the converter, is rarely discussed. This paper presents the analysis of the impact of the lightning surge on a 10 kV SiC MOSFET-based 13.8 kV three-phase four-wire grid-connected converter. The IEEE arrester model and the combined wave generator model in IEC 61000-4-5 standard are used to evaluate the inrush current, DC-link overvoltage, and component-to-ground potential of the converter. Analysis and simulation results have been provided to demonstrate the impact of lightning on the grid-connected converter. It is found that large inrush current occurs due to the small filter inductance, and the neutral-to-ground impedance impacts both the inrush current and the neutral point-to-ground potential.

Li, Haiguo↗

DOE OSTI2021

An Inrush Current Limit Method for SiC-based Multi-level Grid-connected Converter During Low-Voltage Ride-Through

Low-voltage ride-through is one of the grid requirements for grid-connected converters, and during the transient of grid voltage change, a large inrush current could be induced due to the control delay of the converter. This inrush current is more severe in SiC-based multi-level converters due to the small filter inductance, which is selected based on harmonics consideration. In this paper, a PWM mask method is used to limit the inrush current of a cascaded H-bridge-based grid-connected converter during the transient of grid voltage change. Simulation and experiment results are provided to validate this method.

Li, Haiguo↗

DOE OSTI2021

Analytical Expression for DC Link Capacitor Current in a Cascaded H-Bridge Multi-Level Active Front-End Converter

cascaded H-bridge, carrier-based PWM, dc-link capa↗

DOE OSTI2020

Modular, multi-channel, interleaved power converters

A multi-phase power converter includes two or more multi-phase, bi-directional, multi-level, switching power converter subcircuits, connected in parallel at respective AC and DC sides, so as to provide a multi-channel, bi-directional, multi-level configuration. The AC sides of the switching converter subcircuits are directly coupled to one another and to a multi-phase AC input via series interface reactors, and the DC sides of the switching converter subcircuits are directly connected to one another and to a common split-capacitor bank at each level of the multi-level outputs of the switching converter subcircuits. A control circuit is configured to selectively control one or more switching semiconductor devices in each of the switching converter subcircuits. In some embodiments, the control circuit includes a closed-loop zero-sequence controller and a zero-sequence generator configured to eliminate circulating current among the switching converter subcircuits and to balance voltages across levels of the common split-capacitor bank.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2023

Ampaire ARPA-e Electric Flight Testbed

A hybrid-electric aircraft flying testbed was developed in this program with the intent to serve as a dedicated, enduring testbed to test and evaluate ARPA-e CIRCUITS Program and other electrified aviation technologies in relevant flight environments. This testbed enabled rapid development cycles of novel and innovative technologies in the electrified aviation space, maturing them from a research lab environment to flying in an aircraft. By providing research groups with the means to test their transformative technologies in a real-world, aircraft environment, the path to validating the safety and reliability of their technologies for future commercial opportunities was greatly accelerated. Three core technologies were integrated and tested: an inverter/motor drive built by the University of Arkansas, a solid-state circuit breaker (iBreaker) built by the Illinois Institute of Technology, and a Flying Capacitor Multi-level (FCML) DC/DC converter built by the University of California, Berkeley. In each of these cases, the requirements established for safety of flight resulted in a holistic approach to the designs, evoking a deeper understanding of the potential failure modes and mitigations necessary to build a robust and flightworthy system. Further, the integration into a hybrid-electric aircraft de-risked the potential electrical and mechanical issues that cannot easily be experienced or replicated in a lab environment. The experiments were also required to undergo representative temperature, shock, and vibration testing as the FAA prescribes for this category of aircraft, facilitating familiarity with the relevant design and test guidelines necessary to commercialize the technologies. This testbed unlocks the massive potential of core power electronics technologies necessary for a safe, robust, and efficient electric aviation future. With quick iterative design, test, and flight cycles, these core technologies are on a quicker path to technology readiness level maturity and commercialization, enabling a more sustainable future for the aviation industry.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2021

Interleaved multi-channel, multi-level, multi-quadrant DC-DC converters

Direct-current-to-direct-current (DC-DC) power converters that include two or more multi-quadrant, multi-level, DC-DC, switching converter subcircuits, connected in parallel at respective input and output sides, so as to provide a multi-channel, multi-quadrant, multi-level configuration, are disclosed. The DC-DC power converters further include a control circuit configured to control the switching converter subcircuits so that corresponding switching semiconductors in each of the switching converter subcircuits are switched in an interleaved manner. In some embodiments, each of the switching converter subcircuits is a three-level, neutral-point-clamped, four-quadrant DC-DC converter circuit. In other embodiments, each of the switching converter subcircuits is a three-level, neutral-point-clamped, two-quadrant DC-DC converter circuit. In any of these embodiments, a filter capacitor may be connected between across a pair of output terminals at the output sides of the switching converter subcircuits.

Du, Yu↗

DOE OSTI2021

Analysis and design of DC-link capacitor in cascaded H-bridge multilevel active front-end converter

Medium-voltage grid-tied systems often use a cascaded H-bridge multi-level active front-end. In this converter, dc link bus capacitors play an important role in stabilizing the converter and enabling both active and reactive power injections. The present work provides analytical expressions for the capacitor current, which are essential for optimizing system design (especially capacitor size vs. lifetime). Then, the expression is incorporated into the grid connected bidirectional power system model. Consequently, this work contributes to the guiding principles to choose accurate dc link capacitor ratings against grid-side power delivery requirements. DC-link capacitors come with an expiration date which is dependent on the operating power and voltage values. Lack of information about the lifetime of the dc-link capacitor creates uncertainty in the duration of online operation of the converter, thus increasing the probability of a contingency outage. The lifetime of the capacitor can range from only a few seconds of online operation of the station due to under-sizing, to a compromised quality of power flowing through other solid state devices which may not have been designed for the transients that are caused by over-sizing of the dc-link capacitor. A better estimate of the lifetime of these capacitors can help maximize usage and maintain scheduled outages more efficiently, without disruption in service.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2020

Modeling and control of cascaded bridgeless multilevel rectifier under unbalanced load conditions

The goal of this project is to model and control a novel unidirectional cascaded multilevel bridgeless rectifier as an active front end in medium and high voltage applications. This topology has many advantages over a conventional cascaded H-bridge rectifier, such as lower implementation cost, higher reliability, and greater flexibility with similar power quality. The complete design process of the proposed converter is developed step by step in order to meet all the desired objectives. The steady-state mathematical model is used to develop a method for the voltage balancing of dc cells. Power factor analysis is discussed to mathematically derive requirements for the number of partially controlled and fully controlled H-bridges in the proposed H-bridge converter. Power loss, efficiency, and cost comparison studies between the traditional cascaded H-Bridge converter and the proposed bridgeless converter demonstrate the advantages. After exploring various well-established control methods, a novel control strategy is proposed to achieve dc voltage balancing, fast and robust grid synchronization, power factor correction, and elimination of zero crossing current distortion under both balanced and unbalanced load conditions. The converter can also be used for reactive power compensation in a grid tied power system if a sufficient number of fully controlled H-bridge modules are included. Processor-In-the-Loop (PIL) simulation has been the utilized to validate the performance of discrete control structure. Simulation and experimental results validate the models and control method.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2026

BSEC flux towers: CSAT3B and TRH

The data were collected as part of the BSEC project, during the period from June 2025 to May 2026. Directory "broadway" contains data collected on a multi-level flux tower (US-BWf) in the Broadway East neighborhood (1808 North Patterson Park Ave., Baltimore City, MD 21213; LAT: 39o18'40.31'' N; LONG: 76o35'12.43'' W). At each of the four measurement heights (8.5 m, 11.1 m, 13.4 m, 15.9 m), a Campbell Scientific CSAT3B sonic anemometer was operated at 50 Hz to measure virtual temperature (tc) and three velocity components (u: 270 degrees; v: 180 degrees; w: vertical), and a RM Young temperature sensor (model 41382VC) was operated at 1 Hz inside a compact aspirated radiation shield (model 43502) to measure absolute temperature (T) and relative humidity (RH). Inside directory "broadway", directory "netcdf" contains data collected each day in 5-minute chunks that have been converted to NetCDF format (before quality checking), while "4hr" contains data arranged into 4-hour chunks (also in NetCDF format) that have been through basic quality checking steps (treating data points with nonzero diagnostic codes as missing data; fixing six or fewer consecutive missing data points using linear interpolation). Users are recommended to start with data in directory "4hr", while data in directory "netcdf" can be used for reference purposes.

Baltimore↗

NASA NTRS2000

Performance of the OVERFLOW-MLP and LAURA-MLP CFD Codes on the NASA Ames 512 CPU Origin System

The shared memory Multi-Level Parallelism (MLP) technique, developed last year at NASA Ames has been very successful in dramatically improving the performance of important NASA CFD codes. This new and very simple parallel programming technique was first inserted into the OVERFLOW production CFD code in FY 1998. The OVERFLOW-MLP code's parallel performance scaled linearly to 256 CPUs on the NASA Ames 256 CPU Origin 2000 system (steger). Overall performance exceeded 20.1 GFLOP/s, or about 4.5x the performance of a dedicated 16 CPU C90 system. All of this was achieved without any major modification to the original vector based code. The OVERFLOW-MLP code is now in production on the inhouse Origin systems as well as being used offsite at commercial aerospace companies. Partially as a result of this work, NASA Ames has purchased a new 512 CPU Origin 2000 system to further test the limits of parallel performance for NASA codes of interest. This paper presents the performance obtained from the latest optimization efforts on this machine for the LAURA-MLP and OVERFLOW-MLP codes. The Langley Aerothermodynamics Upwind Relaxation Algorithm (LAURA) code is a key simulation tool in the development of the next generation shuttle, interplanetary reentry vehicles, and nearly all "X" plane development. This code sustains about 4-5 GFLOP/s on a dedicated 16 CPU C90. At this rate, expected workloads would require over 100 C90 CPU years of computing over the next few calendar years. It is not feasible to expect that this would be affordable or available to the user community. Dramatic performance gains on cheaper systems are needed. This code is expected to be perhaps the largest consumer of NASA Ames compute cycles per run in the coming year.The OVERFLOW CFD code is extensively used in the government and commercial aerospace communities to evaluate new aircraft designs. It is one of the largest consumers of NASA supercomputing cycles and large simulations of highly resolved full aircraft are routinely undertaken. Typical large problems might require 100s of Cray C90 CPU hours to complete. The dramatic performance gains with the 256 CPU steger system are exciting. Obtaining results in hours instead of months is revolutionizing the way in which aircraft manufacturers are looking at future aircraft simulation work. Figure 2 below is a current state of the art plot of OVERFLOW-MLP performance on the 512 CPU Lomax system. As can be seen, the chart indicates that OVERFLOW-MLP continues to scale linearly with CPU count up to 512 CPUs on a large 35 million point full aircraft RANS simulation. At this point performance is such that a fully converged simulation of 2500 time steps is completed in less than 2 hours of elapsed time. Further work over the next few weeks will improve the performance of this code even further.The LAURA code has been converted to the MLP format as well. This code is currently being optimized for the 512 CPU system. Performance statistics indicate that the goal of 100 GFLOP/s will be achieved by year's end. This amounts to 20x the 16 CPU C90 result and strongly demonstrates the viability of the new parallel systems rapidly solving very large simulations in a production environment.

Taft, James R.↗