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Results for “multiprocessor interconnection”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

Efficient hierarchical interconnection for multiprocessor systems

The authors present a novel approach to the design of a class of hierarchical interconnection networks for multiprocessor systems. This approach, based on an architecture providing separate networks for each level, gives a general and flexible way to construct efficient hierarchical networks. The performance and cost-effectiveness of the resulting networks are analyzed and compared in detail, using both unbuffered and buffered network models. It is shown that, if the design parameters are determined based on the degree of locality, the cost-effectiveness of a hierarchical network can be significantly improved. In addition, the authors investigate how to construct a cost-effectiveness hierarchical network by determining appropriate design parameters. Two associated algorithms are developed for this purpose.

Wei, Sizheng↗
NASA NTRS1987

Considerations for Multiprocessor Topologies

Choosing a multiprocessor interconnection topology may depend on high-level considerations, such as the intended application domain and the expected number of processors. It certainly depends on low-level implementation details, such as packaging and communications protocols. The authors first use rough measures of cost and performance to characterize several topologies. They then examine how implementation details can affect the realizable performance of a topology.

INTERPROCESSOR COMMUNICATION↗
DOE OSTI2024

Foundations for the Future Power System: Inverter-Based Resource Interconnection Standards

As power systems evolve to become reliant on solar, wind, batteries, and other inverter-based resources (IBRs), it is essential that those resources meet certain minimum performance and capability criteria designed to ensure the power system operates stably and reliably. Because those criteria, as enshrined in interconnection standards, take years to develop and are very long lived, they need to account for not only the present state of the power system but also its expected future state over the lifetime of the power plants to which they will apply. In addition, they need to be specific enough to ensure reliability without over specifying and, thereby, impeding innovation. Because power systems are shifting rapidly from a state where IBRs make up a small to medium portion of generation to one where the generation will, at times, come predominantly from IBRs, interconnection standards are especially challenging to develop today. Good interconnection standards can make the power system more reliable and less costly to operate, whereas poorly designed standards can lead to major problems, like the famous German 50.2-Hz problem, which introduced a risk of losing many gigawatts of solar on a frequency excursion and resulted in many IBRs being retrofitted at great cost to mitigate a major system reliability risk. Readying the power system by specifying forward-looking technical minimum functional capabilities for IBRs can be an effective approach to avoid future retrofits.

data models↗
NASA NTRS1986

Viterbi algorithm on a hypercube: Concurrent formulation

The similarity between the Fast Fourier Transform and the Viterbi algorithm is exploited to develop a Concurrent Viterbi Algorithm suitable for a multiprocessor system interconnected as a hypercube. The proposed algorithm can efficiently decode large constraint length convolutional codes, using different degrees of parallelism, and is attractive for VLSI implementation.

Pllara, F.↗
NASA NTRS1993

Software Coherence in Multiprocessor Memory Systems

Processors are becoming faster and multiprocessor memory interconnection systems are not keeping up. Therefore, it is necessary to have threads and the memory they access as near one another as possible. Typically, this involves putting memory or caches with the processors, which gives rise to the problem of coherence: if one processor writes an address, any other processor reading that address must see the new value. This coherence can be maintained by the hardware or with software intervention. Systems of both types have been built in the past; the hardware-based systems tended to outperform the software ones. However, the ratio of processor to interconnect speed is now so high that the extra overhead of the software systems may no longer be significant. This issue is explored both by implementing a software maintained system and by introducing and using the technique of offline optimal analysis of memory reference traces. It finds that in properly built systems, software maintained coherence can perform comparably to or even better than hardware maintained coherence. The architectural features necessary for efficient software coherence to be profitable include a small page size, a fast trap mechanism, and the ability to execute instructions while remote memory references are outstanding.

Bolosky, William Joseph↗
NASA NTRS2000

Performance Monitoring of Distributed Data Processing Systems

Test and checkout systems are essential components in ensuring safety and reliability of aircraft and related systems for space missions. A variety of systems, developed over several years, are in use at the NASA/KSC. Many of these systems are configured as distributed data processing systems with the functionality spread over several multiprocessor nodes interconnected through networks. To be cost-effective, a system should take the least amount of resource and perform a given testing task in the least amount of time. There are two aspects of performance evaluation: monitoring and benchmarking. While monitoring is valuable to system administrators in operating and maintaining, benchmarking is important in designing and upgrading computer-based systems. These two aspects of performance evaluation are the foci of this project. This paper first discusses various issues related to software, hardware, and hybrid performance monitoring as applicable to distributed systems, and specifically to the TCMS (Test Control and Monitoring System). Next, a comparison of several probing instructions are made to show that the hybrid monitoring technique developed by the NIST (National Institutes for Standards and Technology) is the least intrusive and takes only one-fourth of the time taken by software monitoring probes. In the rest of the paper, issues related to benchmarking a distributed system have been discussed and finally a prescription for developing a micro-benchmark for the TCMS has been provided.

Ojha, Anand K.↗
NASA NTRS1996

Stackable Electronic Computer Modules And Interconnections

Design concept for multiprocessor computer system calls for digital electronic processing circuits of various functionalities contained within identically shaped and sized regular polygonal modules interconnected and stacked by use of rings around edges. Rings contain wide-band bus circuits configured to provide connections to adjacent modules in same layer of stack and/or to modules in different layers. Provides flexibility of configuration to implement any of large variety of designs.

Bolotin, Gary S.↗
NASA NTRS1991

A Large-Grain Mapping Approach for Multiprocessor Systems Through Data Flow Model Ph.D. Thesis

A large-grain level mapping method is presented of numerical oriented applications onto multiprocessor systems. The method is based on the large-grain data flow representation of the input application and it assumes a general interconnection topology of the multiprocessor system. The large-grain data flow model was used because such representation best exhibits inherited parallelism in many important applications, e.g., CFD models based on partial differential equations can be presented in large-grain data flow format, very effectively. A generalized interconnection topology of the multiprocessor architecture is considered, including such architectural issues as interprocessor communication cost, with the aim to identify the 'best matching' between the application and the multiprocessor structure. The objective is to minimize the total execution time of the input algorithm running on the target system. The mapping strategy consists of the following: (1) large-grain data flow graph generation from the input application using compilation techniques; (2) data flow graph partitioning into basic computation blocks; and (3) physical mapping onto the target multiprocessor using a priority allocation scheme for the computation blocks.

Kim, Hwa-Soo↗
NASA NTRS1990

Compiler-directed cache management in multiprocessors

The necessity of finding alternatives to hardware-based cache coherence strategies for large-scale multiprocessor systems is discussed. Three different software-based strategies sharing the same goals and general approach are presented. They consist of a simple invalidation approach, a fast selective invalidation scheme, and a version control scheme. The strategies are suitable for shared-memory multiprocessor systems with interconnection networks and a large number of processors. Results of trace-driven simulations conducted on numerical benchmark routines to compare the performance of the three schemes are presented.

Cheong, Hoichi↗
NASA NTRS1987

Clock synchronization of a large multiprocessor system in the presence of malicious faults

An interconnection algorithm is presented for achieving clock synchronization in a multiprocessor system. The system is assumed to be maliciously faulty, i.e., some processors are out of synchronization and lie about their clock state to other intragroup or intergroup processors. A phase-locked clock network design is proposed which groups the clocks in the system into diverse clusters. The clusters are then treated as single clock units from the perspective of the network. The algorithm minimizes the number of interconnections while permitting synchronization of large multiprocessor systems controlling time-critical applications such as aircraft, nuclear reactors and industrial processes.

Shin, Kang G.↗
NASA NTRS1997

The Simulation of Read-time Scalable Coherent Interface

Scalable Coherent Interface (SCI, IEEE/ANSI Std 1596-1992) (SCI1, SCI2) is a high performance interconnect for shared memory multiprocessor systems. In this project we investigate an SCI Real Time Protocols (RTSCI1) using Directed Flow Control Symbols. We studied the issues of efficient generation of control symbols, and created a simulation model of the protocol on a ring-based SCI system. This report presents the results of the study. The project has been implemented using SES/Workbench. The details that follow encompass aspects of both SCI and Flow Control Protocols, as well as the effect of realistic client/server processing delay. The report is organized as follows. Section 2 provides a description of the simulation model. Section 3 describes the protocol implementation details. The next three sections of the report elaborate on the workload, results and conclusions. Appended to the report is a description of the tool, SES/Workbench, used in our simulation, and internal details of our implementation of the protocol.

Li, Qiang↗
NASA NTRS1989

Optical backplane interconnect switch for data processors and computers

An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

Hendricks, Herbert D.↗
NASA NTRS1988

Design consideration in constructing high performance embedded Knowledge-Based Systems (KBS)

As the hardware trends for artificial intelligence (AI) involve more and more complexity, the process of optimizing the computer system design for a particular problem will also increase in complexity. Space applications of knowledge based systems (KBS) will often require an ability to perform both numerically intensive vector computations and real time symbolic computations. Although parallel machines can theoretically achieve the speeds necessary for most of these problems, if the application itself is not highly parallel, the machine's power cannot be utilized. A scheme is presented which will provide the computer systems engineer with a tool for analyzing machines with various configurations of array, symbolic, scaler, and multiprocessors. High speed networks and interconnections make customized, distributed, intelligent systems feasible for the application of AI in space. The method presented can be used to optimize such AI system configurations and to make comparisons between existing computer systems. It is an open question whether or not, for a given mission requirement, a suitable computer system design can be constructed for any amount of money.

Dalton, Shelly D.↗
NASA NTRS1990

Modeling and synthesis of multicomputer interconnection networks

The type of interconnection network employed has a profound effect on the performance of a multicomputer and multiprocessor design. Adequate models are needed to aid in the design and development of interconnection networks. A novel modeling approach using statistical and optimization techniques is described. This method represents an attempt to compare diverse interconnection network designs in a way that allows not only the best of existing designs to be identified but to suggest other, perhaps hybrid, networks that may offer better performance. Stepwise linear regression is used to develop a polynomial surface representation of performance in a (k+1) space with a total of k quantitative and qualitative independent variables describing graph-theoretic characteristics such as size, average degree, diameter, radius, girth, node-connectivity, edge-connectivity, minimum dominating set size, and maximum number of prime node and edge cutsets. Dependent variables used to measure performance are average message delay and the ratio of message completion rate to network connection cost. Response Surface Methodology (RSM) optimizes a response variable from a polynomial function of several independent variables. Steepest ascent path may also be used to approach optimum points.

Standley, Hilda M.↗
NASA NTRS1982

Use of a multiprocessor for control of a robotic system

In the case of complex industrial operations, the use of a multiprocessor for the control of a robotic system has a number of potential advantages over an employment of a single-processor design. In addition to the increased speed of parallel computation, multiprocessors can provide greater reliability. However, the control of a system with a multiprocessor is much more complicated, and requires resolution of a number of design criteria. The degree of coupling, the processor interconnection configuration, and the method of fault detection and correction are factors in the design of a multiprocessor which need to be considered for each particular application. In connection with the present investigation, a five-unit multiprocessor was built to experiment with the multiprocessor control of a robotic system. While the primary application of the multiprocessor involves the control of the Ohio State University (OSU) Hexapod, an 18-degree-of-freedom, motor-driven walking machine, the multiprocessor was designed to be versatile enough for a numbr of other uses.

Klein, C. A.↗
NASA NTRS2006

Interconnect Performance Evaluation of SGI Altix 3700 BX2, Cray X1, Cray Opteron Cluster, and Dell PowerEdge

We study the performance of inter-process communication on four high-speed multiprocessor systems using a set of communication benchmarks. The goal is to identify certain limiting factors and bottlenecks with the interconnect of these systems as well as to compare these interconnects. We measured network bandwidth using different number of communicating processors and communication patterns, such as point-to-point communication, collective communication, and dense communication patterns. The four platforms are: a 512-processor SGI Altix 3700 BX2 shared-memory machine with 3.2 GB/s links; a 64-processor (single-streaming) Cray XI shared-memory machine with 32 1.6 GB/s links; a 128-processor Cray Opteron cluster using a Myrinet network; and a 1280-node Dell PowerEdge cluster with an InfiniBand network. Our, results show the impact of the network bandwidth and topology on the overall performance of each interconnect.

Fatoohi, Rod↗
NASA NTRS1992

A simple modern correctness condition for a space-based high-performance multiprocessor

A number of U.S. national programs, including space-based detection of ballistic missile launches, envisage putting significant computing power into space. Given sufficient progress in low-power VLSI, multichip-module packaging and liquid-cooling technologies, we will see design of high-performance multiprocessors for individual satellites. In very high speed implementations, performance depends critically on tolerating large latencies in interprocessor communication; without latency tolerance, performance is limited by the vastly differing time scales in processor and data-memory modules, including interconnect times. The modern approach to tolerating remote-communication cost in scalable, shared-memory multiprocessors is to use a multithreaded architecture, and alter the semantics of shared memory slightly, at the price of forcing the programmer either to reason about program correctness in a relaxed consistency model or to agree to program in a constrained style. The literature on multiprocessor correctness conditions has become increasingly complex, and sometimes confusing, which may hinder its practical application. We propose a simple modern correctness condition for a high-performance, shared-memory multiprocessor; the correctness condition is based on a simple interface between the multiprocessor architecture and a high-performance, shared-memory multiprocessor; the correctness condition is based on a simple interface between the multiprocessor architecture and the parallel programming system.

Probst, David K.↗