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This seminar will review the development of a comprehensive nanoelectronic modeling tool (NEMO 1-D and NEMO 3-D) and its application to high-speed electronics (resonant tunneling diodes) and IR detectors and lasers (quantum dots and 1-D heterostructures).
Both physical and economic considerations indicate that the scaling era of CMOS will run out of steam around the year 2010. However, physical laws also indicate that it is possible to compute at a rate of a billion times present speeds with the expenditure of only one Watt of electrical power. NASA has long-term needs where ultra-small semiconductor devices are needed for critical applications: high performance, low power, compact computers for intelligent autonomous vehicles and Petaflop computing technology are some key examples. To advance the design, development, and production of future generation micro- and nano-devices, IT Modeling and Simulation Group has been started at NASA Ames with a goal to develop an integrated simulation environment that addresses problems related to nanoelectronics and molecular nanotechnology. Overview of nanoelectronics and nanotechnology research activities being carried out at Ames Research Center will be presented. We will also present the vision and the research objectives of the IT Modeling and Simulation Group including the applications of nanoelectronic based devices relevant to NASA missions.
Both physical and economic considerations indicate that the scaling era of CMOS will run out of steam around the year 2010. However, physical laws also indicate that it is possible to compute at a rate of a billion times present speeds with the expenditure of only one Watt of electrical power. NASA has long-term needs where ultra-small semiconductor devices are needed for critical applications: high performance, low power, compact computers for intelligent autonomous vehicles and Petaflop computing technolpgy are some key examples. To advance the design, development, and production of future generation micro- and nano-devices, IT Modeling and Simulation Group has been started at NASA Ames with a goal to develop an integrated simulation environment that addresses problems related to nanoelectronics and molecular nanotecnology. Overview of nanoelectronics and nanotechnology research activities being carried out at Ames Research Center will be presented. We will also present the vision and the research objectives of the IT Modeling and Simulation Group including the applications of nanoelectronic based devices relevant to NASA missions.
This research focuses on the investigation of strong electron correlations in quasi-one-dimensional oxide nanostructures. The archetypical system consisting of heterostructures formed from an ultrathin layer of LaAlO 3 and TiO 2 -terminated SrTiO 3 offers a unique laboratory for probing strong correlations due to intrinsic richness of the physical system and its ability to be modulated at extreme nanoscale dimensions. Under suitable conditions, SrTiO 3 is known to exhibit a variety of important properties associated with strong electronic correlations, especially superconductivity, magnetism. Understanding the nature of these electronic correlations at fundamental scales, and in reduced spatial dimensions, will provide the scientific basis for new energy technologies, information technologies, and materials. The research program is motivated by recent discoveries and technical advances in the PIs' lab, specifically, (1) pioneering work to create conductive nanostructures to be created in LaAlO 3 /SrTiO 3 heterointerfaces with 2 nm spatial resolution, (2) the discovery of a novel correlated electronic phases in which electrons pair without forming a superconductor, and (3) the demonstrated ability to form high-quality quantum point contacts (QPCs) and achieve ballistic electron transport over micrometer-scales in LaAlO 3 /SrTiO 3 nanowires. The program has three major components. First, we have press forward to develop a full microscopic understanding of the mechanism for electron pairing in LaAlO 3 /SrTiO 3 nanostructures. Understanding the “glue” that leads to pairing and superconductivity in a doped semiconductor will help to form a scientific basis for the correlated oxide nanoelectronics platform being developed. Second, we have used their ability to create well-defined quantum channels in nanowires allows to allow novel “scattering” experiments to be performed that probe fundamentally new quasiparticle excitations using an unprecedented combination of experimental methodologies. Experiments already underway with artificially defined superlattices (5 nm period) demonstrate the feasibility of this approach. Third, we have investigated 1D correlations in proximally coupled nanowires, which are predicted exhibit Majorana-like zero modes in the absence of superconductivity or spin-orbit coupling. These studies provide insight not only into new and emergent phenomena in the rich class of complex oxides, but also fundamental mechanisms of superconductivity and magnetism. Thematically, the research aims to combine some of the most important and interesting challenges in the physics of semiconductor nanostructures and correlated electronic materials. The increased understanding of electron correlations can pave the way to the development of new materials with outstanding or novel properties, which could be relevant for energy-related technologies such as low-power high performance computing, quantum computation, or the development of novel materials.
Lithographic quantum dots (QDs) are highly controllable few-level quantum systems created in semiconductor nanoelectronic devices, with a variety of scientific applications. These include technologically-driven applications like quantum computing and more fundamental applications in which they serve as a platform for exploring basic many-body physics. This document is a brief summary of my Ph.D. research so far and the directions with which I intend to continue it. Highlights include theoretical efforts to understand and design qubits in germanium hole QDs, as well as explorations of the possibility of using QDs coupled to nearby baths for analog simulation of quantum impurity models.
As integrated circuits continue to scale toward the atomic limit, bottom-up processes, such as epitaxial growth, have come to feature prominently in their fabrication. At the same time, chemistry has developed highly tunable molecular semiconductors that can perform the functions of ultimately scaled circuit components. Hybrid techniques that integrate programmable structures comprising molecular components into devices however are sorely lacking. Here we demonstrate a wafer-scale process that directs the localization of a conductive polymer, M w = 20 kg mol –1 polyaniline, from dilute solutions into 50 nm vertical nanogap device architectures using electric-field-driven self-assembly. The resulting metal–polymer–metal junctions were characterized by electron microscopy, Raman spectroscopy and transport measurements demonstrating that our technique is highly selective, assembling conductive polymers only in electrically activated nanogaps. Our results represent a step toward scalable hybrid nanoelectronics that seamlessly integrate established lithographic top-down fabrication with bottom-up synthesized molecular functional circuit components.
Since its invention in 1948, the transistor has revolutionized our everyday life - transistor radios and TV's appeared in the early 1960s, personal computers came into widespread use in the mid-1980s, and cellular phones, laptops, and palm-sized organizers dominated the 1990s. The electronics revolution is based upon transistor miniaturization; smaller transistors are faster, and denser circuitry has more functionality. Transistors in current generation chips are 0.25 micron or 250 nanometers in size, and the electronics industry has completed development of 0.18 micron transistors which will enter production within the next few years. Industry researchers are now working to reduce transistor size down to 0.13 micron - a thousandth of the width of a human hair. However, studies indicate that the miniaturization of silicon transistors will soon reach its limit. For further progress in microelectronics, scientists have turned to nanotechnology to advance the science. Rather than continuing to miniaturize transistors to a point where they become unreliable, nanotechnology offers the new approach of building devices on the atomic scale [see sidebar]. One vision for the next generation of miniature electronics is atomic chain electronics, where devices are composed of atoms aligned on top of a substrate surface in a regular pattern. The Atomic Chain Electronics Project (ACEP) - part of the Semiconductor Device Modeling and Nanotechnology group, Integrated Product Team at the NAS Facility has been developing the theory of understanding atomic chain devices, and the author's patent for atomic chain electronics is now pending.
This report summarizes the research activities supported by the U.S. Department of Energy grant DE-SC-0010399. The goal of this project is to is to develop an on-demand nanoplasmonic platform that combines emerging oxide nanoelectronics with a low-loss semiconductor-friendly plasmonic materials. Toward this goal, several unique heterostructures formed between complex oxides and 2D layered materials have been developed. Based on these material systems, a set of atomic force microscope (AFM) based techniques have been developed that can allow long-living and reversible material phase transitions to be manipulated in nanoscale at room temperature. Using such technique and through interface coupling, we can effectively tune the plasmon propagations in unconventional plasmonic materials such as graphene and VO 2 . In addition, we also discovered a plethora of novel interface enabled electro-optic effects, including the spatial modulation of light using 2DEG, a giant programmable photothermoelectric effects at room temperature, a light induced superconducting transition, and a tunable giant third order optical nonlinearities. These major results are outlined in this report, along with lists of project participants and products.
The III-nitride semiconductors have many attractive properties for field-emission vacuum electronics, including high thermal and chemical stability, low electron affinity, and high breakdown fields. In this work, we report top-down fabricated gallium nitride (GaN)-based nanoscale vacuum electron diodes operable in air, with record ultralow turn-on voltages down to ~0.24 V and stable high field-emission currents, tested up to several microamps for single-emitter devices. We leverage a scalable, top-down GaN nanofabrication method leading to damage-free and smooth surfaces. Gap-dependent and pressure-dependent studies provide new insights into the design of future, integrated nanogap vacuum electron devices. The results show promise for a new class of high-performance and robust, on-chip, III-nitride-based vacuum nanoelectronics operable in air or reduced vacuum.
The understanding and controlled creation of atomic defects in semiconductor transition metal dichalcogenides (TMDs) are highly relevant to their applications in high-performance quantum optics and nanoelectronic devices. Here, we demonstrate a versatile approach in generating single-photon emitters in MoS 2 monolayers using widely attainable UV light. We discover that only defects engendered by UV photons in vacuum exhibit single-photon-emitter characteristics, whereas those created in air lack quantum emission attributes. In combination with theoretical calculations, we assign the defects generated in vacuum to unpassivated sulfur vacancies, whose highly localized midgap states give rise to single-photon emission. In contrast, UV irradiation of the MoS 2 monolayers in air results in oxygen-passivated sulfur vacancies, whose optical properties are likely governed by their pristine band-to-defect band optical transitions. Furthermore, these findings suggest that widely available light sources such as UV light can be utilized for creating quantum photon sources in TMDs.
Abstract The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain a central topic of debate. In this work, we report steep slope switching in MoS 2 transistors back-gated by single-layer polycrystalline PbZr 0.35 Ti 0.65 O 3 . The devices exhibit current switching ratios up to 8 × 10 6 within an ultra-low gate voltage window of $$V_{{{\mathrm{g}}}} = \pm \! 0.5$$ V g = ± 0.5 V and subthreshold swing (SS) as low as 9.7 mV decade −1 at room temperature, transcending the 60 mV decade −1 Boltzmann limit without involving additional dielectric layers. Theoretical modeling reveals the dominant role of the metastable polar states within domain walls in enabling the NC mode, which is corroborated by the relation between SS and domain wall density. Our findings shed light on a hysteresis-free mechanism for NC operation, providing a simple yet effective material strategy for developing low-power 2D nanoelectronics.