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The onboard data processor for OAO 3 flight applications executes instructions at the rate of 2 1/2 billion per day. The computer commands, processes data, and controls telemetry subsystem programs onboard the spacecraft.
With EO-1 Hyperion and MightySat in orbit NASA and the DoD are showing their continued commitment to hyperspectral imaging (HSI). As HSI sensor technology continues to mature, the ever-increasing amounts of sensor data generated will result in a need for more cost effective communication and data handling systems. Lockheed Martin, with considerable experience in spacecraft design and developing special purpose onboard processors, has teamed with Applied Signal & Image Technology (ASIT), who has an extensive heritage in HSI, to develop a real-time and intelligent onboard processing (OBP) system to reduce HSI sensor downlink requirements. Our goal is to reduce the downlink requirement by a factor greater than 100, while retaining the necessary spectral fidelity of the sensor data needed to satisfy the many science, military, and intelligence goals of these systems. Our initial spectral compression experiments leverage commercial-off-the-shelf (COTS) spectral exploitation algorithms for segmentation, material identification and spectral compression that ASIT has developed. ASIT will also support the modification and integration of this COTS software into the OBP. Other commercially available COTS software for spatial compression will also be employed as part of the overall compression processing sequence. Over the next year elements of a high-performance reconfigurable OBP will be developed to implement proven preprocessing steps that distill the HSI data stream in both spectral and spatial dimensions. The system will intelligently reduce the volume of data that must be stored, transmitted to the ground, and processed while minimizing the loss of information.
The general need and requirements for the onboard embedded processors necessary to control and manipulate data in spacecraft systems are discussed. The current known requirements are reviewed from a user perspective, based on current practices in the spacecraft development process. The current capabilities of available processor technologies are then discussed, and these are projected to the generation of spacecraft computers currently under identified, funded development. An appraisal is provided for the current national developmental effort.
Design and operation of onboard spacecraft computer
Improving programming capability of onboard processing system and reducing control circuitry of computer processing unit
The design of a stored program computer for spacecraft use and its application on the fourth Orbiting Astronomical Observatory (OAO) is reported. The computer is a medium scale, parallel machine with a memory capacity of 16384 words of 18 bits each. It possesses a comprehensive instruction repertoire and operates on 45 W of power (including the dc-to-dc converter). The machine operates at a 500-kHz rate and executes an add instruction in 10 microseconds. Its primary functions on OAO C will be auxiliary command storage, spacecraft monitoring and malfunction reporting, data compression and status summary, and possible performance of emergency corrective action for certain anomalous situations.
The application of convolutional codes to protect demultiplexer filter banks is demonstrated analytically for efficient implementations. An overview is given of the parameters for the efficient implementations of filter banks, and real convolutional codes are discussed in terms of DSP operations. Methods for composite filtering and parity generation are outlined, and attention is given to the protection of polyphase filter demultiplexing systems. Real convolutional codes can be applied to protect demultiplexer filter banks by employing two forms of low-rate parity calculation to each filter bank. The parity values are computed either by the output with an FIR parity filter or in parallel with the normal processing by a composite filter. Hardware similarities between the filter bank and the main demultiplexer bank permit efficient redeployment of the processing resources to the main processing function in any configuration.
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Onboard processor servicing spacecraft sensors, programmable from ground, discussing functions and applications
A computer system denoted a change-detection onboard processor (CDOP) is being developed as a means of processing the digitized output of a synthetic-aperture radar (SAR) apparatus aboard an aircraft or spacecraft to generate images showing changes that have occurred in the terrain below between repeat passes of the aircraft or spacecraft over the terrain. When fully developed, the CDOP is intended to be capable of generating SAR images and/or SAR differential interferograms in nearly real time. The CDOP is expected to be especially useful for understanding some large-scale natural phenomena and/or mitigating natural hazards: For example, it could be used for near-real-time observation of surface changes caused by floods, landslides, forest fires, volcanic eruptions, earthquakes, glaciers, and sea ice movements. It could also be used to observe such longer-term surface changes as those associated with growth of vegetation (relevant to estimation of wildfire fuel loads). The CDOP is, essentially, an interferometric SAR processor designed to operate aboard a radar platform.
An interferometric synthetic aperture radar (SAR) onboard processor concept and algorithm has been developed for the Ka-band radar interferometer (KaRIn) instrument on the Surface and Ocean Topography (SWOT) mission. This is a mission- critical subsystem that will perform interferometric SAR processing and multi-look averaging over the oceans to decrease the data rate by three orders of magnitude, and therefore enable the downlink of the radar data to the ground. The onboard processor performs demodulation, range compression, coregistration, and re-sampling, and forms nine azimuth squinted beams. For each of them, an interferogram is generated, including common-band spectral filtering to improve correlation, followed by averaging to the final 1 1-km ground resolution pixel. The onboard processor has been prototyped on a custom FPGA-based cPCI board, which will be part of the radar s digital subsystem. The level of complexity of this technology, dictated by the implementation of interferometric SAR processing at high resolution, the extremely tight level of accuracy required, and its implementation on FPGAs are unprecedented at the time of this reporting for an onboard processor for flight applications.
Natural hazards often result in significant loss of human lives, economic assets and productivity as well as significant damage to the ecosystem. Scientists have reported more frequent and intense natural disasters in recent years, which may well be attributed to climate change. Many of the disaster response efforts were hampered by lack of up-to-date knowledge of the state of the affected areas because damaged infrastructure rendered the areas inaccessible. Radar remote sensing is playing an increasingly critical role in providing timely information to disaster response agencies due to the increasing fidelity and availability of geospatial information products.
The SpaceCube 2.0 is a compact, high performance, low-power onboard processing system that takes advantage of cutting-edge hybrid (CPU/FPGA/DSP) processing elements. The SpaceCube 2.0 design concept includes two commercial Virtex-5 field-programmable gate array (FPGA) parts protected by gradiation hardened by software" technology, and possesses exceptional size, weight, and power characteristics [5x5x7 in., 3.5 lb (approximately equal to 12.7 x 12.7 x 17.8 cm, 1.6 kg) 5-25 W, depending on the application fs required clock rate]. The two Virtex-5 FPGA parts are implemented in a unique back-toback configuration to maximize data transfer and computing performance. Draft computing power specifications for the SpaceCube 2.0 unit include four PowerPC 440s (1100 DMIPS each), 500+ DSP48Es (2x580 GMACS), 100+ LVDS high-speed serial I/Os (1.25 Gbps each), and 2x190 GFLOPS single-precision (65 GFLOPS double-precision) floating point performance. The SpaceCube 2.0 includes PROM memory for CPU boot, health and safety, and basic command and telemetry functionality; RAM memory for program execution; and FLASH/EEPROM memory to store algorithms and application code for the CPU, FPGA, and DSP processing elements. Program execution can be reconfigured in real time and algorithms can be updated, modified, and/or replaced at any point during the mission. Gigabit Ethernet, Spacewire, SATA and highspeed LVDS serial/parallel I/O channels are available for instrument/sensor data ingest, and mission-unique instrument interfaces can be accommodated using a compact PCI (cPCI) expansion card interface. The SpaceCube 2.0 can be utilized in NASA Earth Science, Helio/Astrophysics and Exploration missions, and Department of Defense satellites for onboard data processing. It can also be used in commercial communication and mapping satellites.
Heat pipe performance data taken during the 8 1/2 years of flight of the OAO-C (Copernicus) spacecraft are presented. Three fixed conductance heat pipes (FCHP), each with different wicking concepts (axial groove, pedestal artery, and self-priming spiral artery), and one variable conductance heat pipe (VCHP) are onboard. Aluminum tubes (1/2 in. diameter) rolled into a 48 in. loop containing ultra high purity ammonia as the heat transfer fluid comprise all FCHP, whose purpose is to circumferentially isothermalize the central tube housing the telescope. The VCHP is a hot, non-wicked reservoir concept including a composite artery and methanol heat transfer fluid, and is used to maintain the temperature of the onboard processor. Flight thermal data analysis reveals that no degradation in performance occurred since launch and agrees well with pre-flight data; the onboard processor still shows an offset in control range of 4 F, and the pipes perform the same after 8 1/2 years in orbit.
Development and characteristics of onboard processor system
The Applied Physics Laboratory (APL) has developed a flightworthy custom microprocessor that increases capability and reduces development costs of lightsat science instruments. This device, called the FRISC (FORTH Reduced Instruction Set Computer), directly executes the high-level language called FORTH, which is ideally suited to the multitasking control and data processing environment of a spaceborne instrument processor. The FRISC will be flown as the onboard processor in the Magnetic Field Experiment on the Freja satllite. APL has achieved a significant increase in onboard processing capability with no increase in cost when compared to the magnetometer instrument on Freja's predecessor, the Viking satellite.
This paper reports some interim results relating to an on-going effort to develop an electronic processor for real-time processing of synthetic aperture radar data. An experimental laboratory processor is being developed as a testbed for design of onboard processors for future space missions. This paper describes the configuration of the experimental processor and discusses technical factors pertaining to the design.