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Results for “phase-locking”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS1958

Acquisition and Tracking Behavior of Phase-Locked Loops

Phase-locked or APC loops have found increasing applications in recent years as tracking filters, synchronizing devices, and narrowband FM discriminators. Considerable work has been performed to determine the noise-squelching properties of the loop when it is operating in or near phase lock and is functioning as a linear coherent detector. However, insufficient consideration has been devoted to the non-linear behavior of the loop when it is out of lock and in the process of pulling in. Experimental evidence has indicated that there is a strong tendency for phase-locked loops to achieve lock under most circumstances. However, the analysis which has appeared in the literature iis limited to the acquisition of a constant frequency reference signal with only one phase-locked loop filter configuration. This work represents an investigation of frequency acquisition properties of phase-locked loops for a variety of reference-signal behavior and loop configurations

Viterbi, A. J.↗
NASA NTRS1961

A Threshold Theory for Phase-Locked Loops

A model of a phase-locked loop has been developed which is valid for all signal-to-noise ratios. The model is in the form of a nonlinear feedback system with randomly time-varying parameters. The analysis considers two operating regions. In low signal-to-noise ratio regions, the important consideration is stability. We want to study the asymptotic stability in the mean of a nonlinear system. It follows directly that a necessary condition for asymptotic stability of any nonlinear system is that a linearized model about some equilibrium point be asymptotically stable. By considering all possible equilibrium points, we can find an upper bound on the value of noise density which makes the system unstable. This upper bound represents a threshold value for system operation. In high signal-to-noise ratio regions, our results provide an exact statistical. description of system behavior. Therefore, knowledge of the spectrum of the signal and noise may be used to optimize the system configuration.

Van Trees, H. L.↗
NASA NTRS1972

An all digital phase locked loop for FM demodulation.

A phase-locked loop designed with all-digital circuitry which avoids certain problems, and a digital voltage controlled oscillator algorithm are described. The system operates synchronously and performs all required digital calculations within one sampling period, thereby performing as a real-time special-purpose computer. The SNR ratio is computed for frequency offsets and sinusoidal modulation, and experimental results verify the theoretical calculations.

Greco, J.↗
NASA NTRS1974

Synthesis and evaluation of phase detectors for active bit synchronizers

Self-synchronizing digital data communication systems usually use active or phase-locked loop (PLL) bit synchronizers. The three main elements of PLL synchronizers are the phase detector, loop filter, and the voltage controlled oscillator. Of these three elements, phase detector synthesis is the main source of difficulty, particularly when the received signals are demodulated square-wave signals. A phase detector synthesis technique is reviewed that provides a physically realizable design for bit synchronizer phase detectors. The development is based upon nonlinear recursive estimation methods. The phase detector portion of the algorithm is isolated and analyzed.

Mcbride, A. L.↗
NASA NTRS1987

Clock synchronization of a large multiprocessor system in the presence of malicious faults

An interconnection algorithm is presented for achieving clock synchronization in a multiprocessor system. The system is assumed to be maliciously faulty, i.e., some processors are out of synchronization and lie about their clock state to other intragroup or intergroup processors. A phase-locked clock network design is proposed which groups the clocks in the system into diverse clusters. The clusters are then treated as single clock units from the perspective of the network. The algorithm minimizes the number of interconnections while permitting synchronization of large multiprocessor systems controlling time-critical applications such as aircraft, nuclear reactors and industrial processes.

Shin, Kang G.↗