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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

The Regenerative Current Mirror: A Very Low Power Front-End Amplifier for Silicon Pixel Detectors

In pixelized detectors, reducing power consumption in the front- end ASIC chips becomes a crucial demand. Optimization based on mature pre-amplifier schemes today is unlikely to bring sufficient improvements. A new CMOS front-end gain stage topology with very low power consumption called regenerative current mirror is developed to fulfill the demand. The circuit takes advantage of high-speed performance of current amplification while operating with relatively low bias current. The regenerative current mirror uses a NMOS current mirror and a PMOS current mirror, both with nominal gain of 1, to form a loop-back topology that provides a positive feedback. An NMOS FET with an external adjustable voltage applied to it gate terminal is used to limit open loop gain of the current mirrors to be slightly lower than 1. This yields a net gain of the positive feedback loop to be much larger than 1 while operating the current mirrors under relatively low bias currents. Simulation shows that in 65 nm fabrication process, the power consumption of the gain stages suitable for silicon pixel detectors can be controlled < 10 micro-Watts per channel. Another novel low-power circuit called Pseudo-Thyristor presented in another document will replace traditional discriminator and the Regenerative Current Mirror plus Pseudo- Thyristor will provide a full solution for the silicon pixel low-power frontend ASIC.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

The Regenerative Current Mirror: A Very Low Power Front-End Amplifier for Silicon Pixel Detectors

In pixelized detectors, reducing power consumption in the front end ASIC chips becomes a crucial demand. Optimization based on mature pre-amplifier schemes today is unlikely to bring sufficient improvements. A new CMOS front-end gain stage topology with very low power consumption called regenerative current mirror is developed to fulfill the demand. The circuit takes advantage of high speed performance of current amplification while operating with relatively low bias current. The regenerative current mirror uses a NMOS current mirror and a PMOS current mirror, both with nominal gain of 1, to form a loop-back topology that provides a positive feedback. An NMOS FET with an external adjustable voltage applied to it gate terminal is used to limit open loop gain of the current mirrors to be slightly lower than 1. This yields a net gain of the positive feedback loop to be much larger than 1 while operating the current mirrors under relatively low bias currents. Simulation shows that in 65 nm fabrication process, the power consumption of the gain stages suitable for silicon pixel detectors can be controlled < 10 micro-Watts per channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

The CMS Phase-1 Pixel Detector Upgrade

The CMS detector at the CERN LHC features a silicon pixel detector as its innermost subdetector. The original CMS pixel detector has been replaced with an upgraded pixel system (CMS Phase-1 pixel detector) in the extended year-end technical stop of the LHC in 2016/2017. The upgraded CMS pixel detector is designed to cope with the higher instantaneous luminosities that have been achieved by the LHC after the upgrades to the accelerator during the first long shutdown in 2013–2014. Compared to the original pixel detector, the upgraded detector has a better tracking performance and lower mass with four barrel layers and three endcap disks on each side to provide hit coverage up to an absolute value of pseudorapidity of 2.5. This paper describes the design and construction of the CMS Phase-1 pixel detector as well as its performance from commissioning to early operation in collision data-taking.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Strategies for on-chip digital data compression for X-ray pixel detectors

Here, the continued desire for X-ray pixel detectors with higher frame rates will stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates in the 1 MHz regime. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-counting and charge-integrating pixel detectors. In particular, we describe a novel in-pixel compression scheme that converts from analog to digital converter units to encoded photon counts near the photon Poisson noise level and achieves a compression ratio of >1.5x independent of the dataset. In addition, we describe a simple yet efficient zero-suppression compression scheme called "zeromask" (ZM) located at the ASIC's edge before streaming data off the ASIC chip. ZM achieves average compression ratios of >4x, >7x, and >8x for high-energy X-ray diffraction, ptychography, and X-ray photon correlation spectroscopy datasets, respectively. We present the conceptual designs, register-transfer level block diagrams, and the physical ASIC implementation of these compression schemes in 65 nm CMOS. When combined, these two digital compression schemes could increase the effective off-chip bandwidth by a factor of 6-12x.

47 OTHER INSTRUMENTATION↗
NASA NTRS2014

Verification of Dosimetry Measurements with Timepix Pixel Detectors for Space Applications

The current capabilities of modern pixel-detector technology has provided the possibility to design a new generation of radiation monitors. Timepix detectors are semiconductor pixel detectors based on a hybrid configuration. As such, the read-out chip can be used with different types and thicknesses of sensors. For space radiation dosimetry applications, Timepix devices with 300 and 500 microns thick silicon sensors have been used by a collaboration between NASA and University of Houston to explore their performance. For that purpose, an extensive evaluation of the response of Timepix for such applications has been performed. Timepix-based devices were tested in many different environments both at ground-based accelerator facilities such as HIMAC (Heavy Ion Medical Accelerator in Chiba, Japan), and at NSRL (NASA Space Radiation Laboratory at Brookhaven National Laboratory in Upton, NY), as well as in space on board of the International Space Station (ISS). These tests have included a wide range of the particle types and energies, from protons through iron nuclei. The results have been compared both with other devices and theoretical values. This effort has demonstrated that Timepix-based detectors are exceptionally capable at providing accurate dosimetry measurements in this application as verified by the confirming correspondence with the other accepted techniques.

Kroupa, M.↗
DOE OSTI2022

The Timepix4 analog front-end design: Lessons learnt on fundamental limits to noise and time resolution in highly segmented hybrid pixel detectors

This manuscript describes the optimization of the front-end readout electronics for high granularity hybrid pixel detectors. The theoretical study aims at minimizing the noise and jitter. The model presented here is validated with both circuit post layout simulations and measurements on the Timepix4 Application Specific Integrated Circuit (ASIC). The analog front-end circuit and the procedure to optimize the dimensions of the main transistors are described with detail. The Timepix4 is the most recent ASIC designed in the framework of the Medipix4 Collaboration. It was manufactured in 65nm CMOS process, and consists of a four side buttable matrix of 448 × 512 pixels with 55µm pitch. The analog front-end has a gain of ~36mV/ke - when configured in High Gain Mode, and ~20mV/ke - when configured in Low Gain Mode. The Equivalent Noise Charge (ENC) is ~68e - rms and ~80e - rms in High Gain Mode and in Low Gain Mode respectively. In event driven mode the incoming hits can be time stamped within a ~ 200ps time bin and the chip can deal with a maximum flux of ~ 3.6MHzmm –2 s –1 . In photon counting mode, the chip can deal with up to ~ 5GHzmm –2 s –1 . The routine designed to optimize the Timepix4 front-end is then used to analyze the performance limits in terms of jitter and noise for Charge Sensitive Amplifiers in pixel detectors.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Particle showers detected on ISS in Timepix pixel detectors

We detect regular particle showers in several compact pixel detectors, distributed over the International Space Station. These showers are caused by high energy galactic cosmic rays, with energies often in the 10 s of TeV or higher. We survey the frequency of these events, their dependence on location on ISS, and their independence of the location of ISS, on its orbit. The Timepix detectors used allow individual particle tracks to be resolved, providing a possibility to perform physical analysis of shower events, which we demonstrate. In terms of radiation dosimetry, these showers indicate certain possible limitations of traditional dosimetric measures, in that (a) the dose measured in small sensor may be less than that received in a larger distribution of matter, such as a human and (b) the spatial and temporal extent of these events represents a regime of poorly documented biological response.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2020

RD53A: A large-scale prototype chip for the phase II upgrade in the serially powered HL-LHC pixel detectors

The phase II upgrade of the HL-LHC experiments within the LHC intends to deepen the studies of the Higgs boson and to allow the discovery of further particles by adding an integrated luminosity of about 4000 fb -1 over 10 years of operation. This upgrade would overwhelm the installed pixel detector readout chips with higher hit rates and radiation levels than ever before. To match these extreme requirements the RD53 collaboration, a joint effort between ATLAS and CMS, developed RD53A, a new generation pixel detector readout chip prototype manufactured in a 65 nm CMOS technology. It is half the size of the final pixel chips and designed to meet requirements in the face of 3 GHz/cm 2 hit rate after irradiation to 500 Mrad. The detector is able to use 50×50 μm 2 or 25×100 μm 2 pixels with high readout speed of up to 4 links per chip with 1.28 Gbit/s each. Shunt–LDO regulators integrated on the bottom of the chip provide the required voltages to the two power domains, analog and digital. These regulators enable serial powering of the pixel modules, which is the only feasible, radiation hard scheme to ensure acceptable power cable losses and to stay within the material budget for the future pixel detectors. Finally, an overview of the status and challenges of serial powering and the Shunt–LDO regulator development will be given.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Intelligent Pixel Detectors: Towards a Radiation Hard ASIC with On-Chip Machine Learning in 28 nm CMOS

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. We are developing a radiation hard readout integrated circuit (ROIC) in 28nm CMOS with on-chip machine learning (ML) for future intelligent pixel detectors. We will show track parameter predictions using a neural network within a single layer of silicon and hardware tests on the first tape-outs produced with TSMC. Preliminary results indicate that reading out featurized clusters from particles above a modest momentum threshold could enable using pixel information at 40 MHz.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Rad-hard readout system for Timepix3 Hybrid Pixel Detectors

The Beam Gas Ionisation (BGI) profile monitor, located in the Proton Synchrotron (PS) and Super Proton Synchrotron (SPS) at CERN, requires a radiation-tolerant readout system to transfer data from the challenging accelerator surroundings to the back-end for processing. The system needs to control and acquire data from four Timepix3 Hybrid Pixel Detectors (HPDs) located directly inside the beam pipe, a highly radioactive environment. It must ensure reliability given limited hardware access and preserve signal integrity for the high-speed data (32 channels at 320 MHz). However, due to the unavailability of a suitable rad-hard Timepix3 readout, the Beam Instrumentation PiXeL (BIPXL) readout system was designed to meet these requirements. This system employs radiation-hardened components such as the GBTx and the FEASTMP, both developed at CERN. It will be compatible with forthcoming hybrid pixel detector initiatives in similarly harsh radiation conditions.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Conceptual study of a two-layer silicon pixel detector to tag the passage of muons from cosmic sources through quantum processors

Abstract Recent studies in quantum computing have shown that quantum error correction with large numbers of physical qubits are limited by ionizing radiation from high-energy particles. Depending on the physical setup of the quantum processor, the contribution of muons from cosmic sources can constitute a significant fraction of these interactions. As most of these muons are difficult to stop, we perform a conceptual study of a two-layer silicon pixel detector to tag their hits on a solid-state quantum processor instead. With a typical dilution refrigerator geometry model, we find that efficiencies greater than 50% are most likely to be achieved if at least one of the layers is operated at the deep-cryogenic (<1 K) flanges of the refrigerator. Following this finding, we further propose a novel research program that could allow the development of silicon pixel detectors that are fast enough to provide input to quantum error correction algorithms, can operate at deep-cryogenic temperatures, and have very low power consumption.

Instruments & Instrumentation↗
NASA NTRS2002

Charge Sharing and Charge Loss in a Cadmium-Zinc-Telluride Fine-Pixel Detector Array

Because of its high atomic number, room temperature operation, low noise, and high spatial resolution a Cadmium-Zinc-Telluride (CZT) multi-pixel detector is ideal for hard x-ray astrophysical observation. As part of on-going research at MSFC (Marshall Space Flight Center) to develop multi-pixel CdZnTe detectors for this purpose, we have measured charge sharing and charge loss for a 4x4 (750micron pitch), lmm thick pixel array and modeled these results using a Monte-Carlo simulation. This model was then used to predict the amount of charge sharing for a much finer pixel array (with a 300micron pitch). Future work will enable us to compare the simulated results for the finer array to measured values.

Gaskin, J. A.↗
DOE OSTI2023

PIXEL2020: Tenth International Workshop on Semiconductor Pixel Detectors for Particles and Imaging

This workshop covers various topics related to pixel detector technology. Development and applications will be discussed for charged particle tracking in High Energy Physics, Nuclear Physics, Astrophysics, and X-ray imaging in Astronomy, Biology, Medicine and Material Science. The conference program will also include reports on front and back end electronics, radiation effects, low mass mechanics and construction techniques, and new technologies such as monolithic and 3D integrated detectors.

Sally, Seidel↗
NASA NTRS1992

Modulation transfer function measurement technique for small-pixel detectors

A modulation transfer function (MTF) measurement technique suitable for large-format, small-pixel detector characterization has been investigated. A volume interference grating is used as a test image instead of the bar or sine wave target images normally used. This technique permits a high-contrast, large-area, sinusoidal intensity distribution to illuminate the device being tested, avoiding the need to deconvolve raw data with imaging system characteristics. A high-confidence MTF result at spatial frequencies near 200 cycles/mm is obtained. We present results at several visible light wavelengths with a 6.8-micron-pixel CCD. Pixel response functions are derived from the MTF results.

Marchywka, Mike↗
DOE OSTI2025

Detector pixel calibration of time-of-flight neutron diffractometers accelerated by machine learning

Modern time-of-flight neutron diffractometers at spallation neutron source are equipped with two dimensional detectors with fine pixelations. The flight path of neutrons from the moderator to the sample and to the detector needs to be precisely calibrated at detector pixel level using standard powders so the diffraction data from all the detector pixels can be correctly time-focused to produce high resolution diffraction peaks. The number of pixels can reach to millions which makes a single-pixel calibration process time-consuming, or even impossible, with conventional fitting routine. Here we presented a machine learning aided calibration process via a “training and predict” process by training machine learning models with the relations between the individual pixel time-of-flight diffraction pattern and fitted diffraction constant. The training models take a portion of the available pixels to predict the diffraction constants precisely and rapidly for massive pixel diffraction patterns.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Flatfielding of hybrid pixel detectors in tender x-ray scattering

The ability of the soft matter interfaces beamline at National Synchrotron Light Source II to access x-ray energy in the tender x-ray regime, i.e., from 2.1 to 5 keV, enables new resonant x-ray scattering studies at the sulfur K-edge and others. We present a new approach to correct data acquired in the tender x-ray regime with a Pilatus3 detector in order to improve the data quality and to correct the various artifacts inherent to hybrid pixel detectors, such as variations in modules’ efficiency or noisy detector module junctions. Further, this new flatfielding significantly enhances the data quality and enables detection of weak scattering signals.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗