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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2015

Standards for Radiation Effects Testing: Ensuring Scientific Rigor in the Face of Budget Realities and Modern Device Challenges

An overview is presented of the space radiation environment and its effects on electrical, electronic, and electromechanical parts. Relevant test standards and guidelines are listed. Test standards and guidelines are necessary to ensure best practices, minimize and bound systematic and random errors, and to ensure comparable results from different testers and vendors. Test standards are by their nature static but exist in a dynamic environment of advancing technology and radiation effects research. New technologies, failure mechanisms, and advancement in our understanding of known failure mechanisms drive the revision or development of test standards. Changes to standards must be weighed against their impact on cost and existing part qualifications. There must be consensus on new best practices. The complexity of some new technologies exceeds the scope of existing test standards and may require development of a guideline specific to the technology. Examples are given to illuminate the value and limitations of key radiation test standards as well as the challenges in keeping these standards up to date.

Test Standard↗
NASA NTRS2005

PDSOI and Radiation Effects: An Overview

Bulk silicon substrates are a common characteristic of nearly all commercial, Complementary Metal-Oxide-Semiconductor (CMOS), integrated circuits. These devices operate well on Earth, but are not so well received in the space environment. An alternative to bulk CMOS is the Silicon-On-Insulator (SOI), in which a &electric isolates the device layer from the substrate. SO1 behavior in the space environment has certain inherent advantages over bulk, a primary factor in its long-time appeal to space-flight IC designers. The discussion will investigate the behavior of the Partially-Depleted SO1 (PDSOI) device with respect to some of the more common space radiation effects: Total Ionized Dose (TID), Single-Event Upsets (SEUs), and Single-Event Latchup (SEL). Test and simulation results from the literature, bulk and epitaxial comparisons facilitate reinforcement of PDSOI radiation characteristics.

Forgione, Joshua B.↗
NASA NTRS2002

Evaluation of Data Retention and Imprint Characteristics of FRAMs Under Environmental Stresses for NASA Applications

A major reliability issue for all advanced nonvolatile memory (NVM) technology devices including FRAMs is the data retention characteristics over extended period of time, under environmental stresses and exposure to total ionizing dose (TID) radiation effects. For this testing, 256 Kb FRAMs in 28-pin plastic DIPS, rated for industrial grade temperature range of -40 C to +85 C, were procured. These are two-transistor, two-capacitor (2T-2C) design FRAMs. In addition to data retention characteristics, the parts were also evaluated for imprint failures, which are defined as the failure of cells to change from a "preferred" state, where it has been for a significant period of time to an opposite state (e.g., from 1 to 0, or 0 to 1). These 256 K FRAMs were subjected to scanning acoustic microscopy (C-SAM); 1,000 temperature cycles from -65 C to +150 C; high temperature aging at 150 C, 175 C, and 200 C for 1,000 hours; highly accelerated stress test (HAST) for 500 hours; 1,000 hours of operational life test at 125 C; and total ionizing dose radiation testing. As a preconditioning, 10 K read/write cycles were performed on all devices. Interim electrical measurements were performed throughout this characterization, including special imprint testing and final electrical testing. Some failures were observed during high temperature aging test at 200 C, during HAST testing, and during 1,000 hours of operational life at 125 C. The parts passed 10 Krad exposure, but began showing power supply current increases during the dose increment from 10 Krad to 30 Krad, and at 40 Krad severe data retention and parametric failures were observed. Failures from various environmental group testing are currently being analyzed.

Sharma, Asbok K.↗
NASA NTRS2000

Evaluation of Data Retention and Imprint Characteristics of FRAMs Under Environmental Stresses for NASA Applications

A major reliability issue for all advanced nonvolatile memory (NVM) technology devices including FRAMs (Ferroelectric random access memories) is the data retention characteristics over extended period of time, under environmental stresses and exposure to total ionizing dose (TID) radiation effects. For this testing, 256 Kb FRAMs in 28-pin plastic DIPS, rated for industrial grade temperature range of -40 C to +85 C, were procured. These are two-transistor, two-capacitor (2T-2C) design FRAMs. In addition to data retention characteristics, the parts were also evaluated for imprint failures, which are defined as the failure of cells to change from a "preferred" state, where it has been for a significant period of time to an opposite state (e.g., from 1 to 0, or 0 to 1). These 256 K FRAMs were subjected to scanning acoustic microscopy (C-SAM); 1,000 temperature cycles from -65 C to +150 C; high temperature aging at 150 C, 175 C, and 200 C for 1,000 hours; highly accelerated stress test (HAST) for 500 hours; 1,000 hours of operational life test at 125 C; and total ionizing dose radiation testing. As a preconditioning, 10 K read/write cycles were performed on all devices. Interim electrical measurements were performed throughout this characterization, including special imprint testing and final electrical testing. Some failures were observed during high temperature aging test at 200 C, during HAST testing, and during 1,000 hours of operational life at 125 C. The parts passed 10 Krad exposure, but began showing power supply current increases during the dose increment from 10 Krad to 30 Krad, and at 40 Krad severe data retention and parametric failures were observed. Failures from various environmental group testing are currently being analyzed.

Sharma, Ashok K.↗
NASA NTRS1993

Design of CMOS logic gates for TID radiation

The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

Attia, John Okyere↗
NASA NTRS2011

Radiation-Tolerant, SpaceWire-Compatible Switching Fabric

Current and future near-Earth and deep space exploration programs and space defense programs require the development of robust intra-spacecraft serial data transfer electronics that must be reconfigurable, fault-tolerant, and have the ability to operate effectively for long periods of time in harsh environmental conditions. Existing data transfer systems based on state-of-the-art serial data transfer protocols or passive backplanes are slow, power-hungry, and poorly reconfigurable. They provide limited expandability and poor tolerance to radiation effects and total ionizing dose (TID) in particular, which presents harmful threats to modern submicron electronics. This novel approach is based on a standard library of differential cells tolerant to TID, and patented, multi-level serial interface architecture that ensures the reliable operation of serial interconnects without application of a data-strobe or other encoding techniques. This proprietary, high-speed differential interface presents a lowpower solution fully compatible with the SpaceWire (SW) protocol. It replaces a dual data-strobe link with two identical independent data channels, thus improving the system s tolerance to harsh environments through additional double redundancy. Each channel incorporates an automatic line integrity control circuitry that delivers error signals in case of broken or shorted lines.

Katzman, Vladimir↗
NASA NTRS1991

The NASA Microelectronics Space Radiation Effects Program (MSREP) at the Jet Propulsion Laboratory

The primary objective of the Microelectronics Space Radiation Effects Program (MSREP) at the Jet Propulsion Laboratory (JPL) is to assist NASA in the selection of radiation hardened microelectronic parts for insertion in NASA space systems through radiation testing and research. Prior to presenting examples of the research and testing on Single Event Effects (SEE) and Total Ionizing Dose (TID) effects, the space radiation environment and radiation requirements for the CRAFT/Cassini program, a typical JPL space project, are discussed.

Barnes, C.↗
NASA NTRS2021

Total Ionizing Dose (TID) Testing of the PA10 Power Operational Amplifier

This study was undertaken to determine the total ionizing dose (TID) sensitivity of the PA10 Power Op Amp Manufactured by APEX (figure 1), which is a candidate for use on the LDCM TIRS instrument. The test was conducted with interest in both parametric degradation and functional failure in the configuration like that of the TIRS application. (See figure 2). The DUT was irradiated in a stepwise fashion, with parametric and functional degradation measured between steps. The parts were irradiated with gamma rays at a low dose rate (~0.01 rads(Si)/sec.).

total ionizing dose (TID)↗
NASA NTRS2020

In Situ Testing Methods for Mixed-Mode Harsh Environments

A review of the radiation effects investigation capabilities of the JPL Dynamitron Accelerator Facility are discussed. A process for its use in performing total ionizing dose (TID) studies are outlined. The results of radiation effects in complicated test systems where device effects may occur due to local system irradiation are also presented.

Wong, A. T.↗
NASA NTRS1998

An Adaptable Power System with Software Control Algorithm

A low cost, flexible and modular spacecraft power system design was developed in response to a call for an architecture that could accommodate multiple missions in the small to medium load range. Three upcoming satellites will use this design, with one launch date in 1999 and two in the year 2000. The design consists of modular hardware that can be scaled up or down, without additional cost, to suit missions in the 200 to 600 Watt orbital average load range. The design will be applied to satellite orbits that are circular, polar elliptical and a libration point orbit. Mission unique adaptations are accomplished in software and firmware. In designing this advanced, adaptable power system, the major goals were reduction in weight volume and cost. This power system design represents reductions in weight of 78 percent, volume of 86 percent and cost of 65 percent from previous comparable systems. The efforts to miniaturize the electronics without sacrificing performance has created streamlined power electronics with control functions residing in the system microprocessor. The power system design can handle any battery size up to 50 Amp-hour and any battery technology. The three current implementations will use both nickel cadmium and nickel hydrogen batteries ranging in size from 21 to 50 Amp-hours. Multiple batteries can be used by adding another battery module. Any solar cell technology can be used and various array layouts can be incorporated with no change in Power System Electronics (PSE) hardware. Other features of the design are the standardized interfaces between cards and subsystems and immunity to radiation effects up to 30 krad Total Ionizing Dose (TID) and 35 Mev/cm(exp 2)-kg for Single Event Effects (SEE). The control algorithm for the power system resides in a radiation-hardened microprocessor. A table driven software design allows for flexibility in mission specific requirements. By storing critical power system constants in memory, modifying the system code for other programs is simple. These constants can be altered also by ground command, or in response to an anomolous event. All critical power system functions have backup hardware functions to prevent a software or computer glitch from propagating. A number of battery charge control schemes can be implemented by selecting the proper control terms in the code. The architecture allows the design engineer to tune the system response to various system components and anticipated load profiles without costly alterations. A design trade was made with the size, weight and power dissipation of the electronics versus the performance of the power bus to load variations. Linear, fine control is maintained with a streamlined electronics design. This paper describes the hardware design as well as the software control algorithm. The challenges of closing the system control loop digitally is discussed. Control loop margin and power system performance is presented. Lab measurements are shown and compared to the system response of a hardware model running actual flight software.

Castell, Karen↗
DOE OSTI2020

Layer-Dependent Bit Error Variation in 3-D NAND Flash Under Ionizing Radiation

In this paper, we studied the total ionization dose (TID) effects on the multilevel-cell (MLC) 3-D NAND flash memory using Co-60 gamma radiation. We found a significant page-to-page bit error variation within a physical memory block of the irradiated memory chip. Our analysis showed that the origin of the bit error variation is the unique vertical layer-dependent TID response of the 3-D NAND. We found that the memory pages located at the upper and lower layers of the 3-D stack show higher fails compared to the middle-layer pages of a given memory block. We confirmed our findings by comparing radiation response of four different chips of the same specification. In addition, we compared the TID response of the MLC 3-D NAND with that of the 2-D NAND chip, which showed less page-to-page variation in bit error within a given memory block. We discuss the possible application of our findings for the radiation-tolerant smart memory controller design.

3-D NAND flash↗
NASA NTRS2008

Guideline for ground radiation testing of microprocessors in the space radiation environment

The goal of this work is to develop a guideline that is applicable to processors that are potentially useful in space. Thus, the guideline does not consider very high performance processors that are intended for server or high-performance applications where very large amounts of power are tolerated to gain performance because it would be impractical to use such high-power devices in typical space applications. This guide is intended to support insertion of these microprocessors into spaceflight applications and to recommend ground test protocols. The first guideline principle that should be followed is a serious concurrent engineering approach for down selecting space-qualified microprocessors. This requires that the design engineer seek the support of a radiation effects expert who understands total ionizing dose (TID) and single-event effects (SEEs) issues for microprocessors as applied to the system in question.

Irom, Farokh↗