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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Comparative evaluation of analogue front-end designs for the CMS Inner Tracker at the High Luminosity LHC

The CMS Inner Tracker, made of silicon pixel modules, will be entirely replaced prior to the start of the High Luminosity LHC period. One of the crucial components of the new Inner Tracker system is the readout chip, being developed by the RD53 Collaboration, and in particular its analogue front-end, which receives the signal from the sensor and digitizes it. Three different analogue front-ends (Synchronous, Linear, and Differential) were designed and implemented in the RD53A demonstrator chip. A dedicated evaluation program was carried out to select the most suitable design to build a radiation tolerant pixel detector able to sustain high particle rates with high efficiency and a small fraction of spurious pixel hits. The test results showed that all three analogue front-ends presented strong points, but also limitations. The Differential front-end demonstrated very low noise, but the threshold tuning became problematic after irradiation. Moreover, a saturation in the preamplifier feedback loop affected the return of the signal to baseline and thus increased the dead time. The Synchronous front-end showed very good timing performance, but also higher noise. For the Linear front-end all of the parameters were within specification, although this design had the largest time walk. This limitation was addressed and mitigated in an improved design. The analysis of the advantages and disadvantages of the three front-ends in the context of the CMS Inner Tracker operation requirements led to the selection of the improved design Linear front-end for integration in the final CMS readout chip.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Tolerating memory stack failures in multi-stack systems

Memory management circuitry and processes operate to improve reliability of a group of memory stacks, providing that if a memory stack or a portion thereof fails during the product's lifetime, the system may still recover with no errors or data loss. A front-end controller receives a block of data requested to be written to memory, divides the block into sub-blocks, and creates a new redundant reliability sub-block. The sub-blocks are then written to different memory stacks. When reading data from the memory stacks, the front-end controller detects errors indicating a failure within one of the memory stacks, and recovers corrected data using the reliability sub-block. The front-end controller may monitor errors for signs of a stack failure and disable the failed stack.

Mappouras, Georgios↗
DOE OSTI2025

Leveraging the Run 3 experience for the evolution of the ATLAS software-based readout towards HL-LHC

The High-Luminosity Large Hadron Collider (HL-LHC), scheduled to start operating in 2030, aims to increase the instantaneous luminosity by a factor of 10 compared to the LHC. To match this increase, the ATLAS experiment has been implementing a major upgrade program divided into two phases. The first phase (Phase-I), completed in 2022, introduced new trigger and detector systems that have been used during the Run 3 data taking period which began in July 2022. These systems have been used in conjunction with the new Data Acquisition (DAQ) Readout system, based on a software application called Software Readout Driver (SW ROD). SW ROD receives and aggregates data from the front-end electronics via the Front-End Link eXchange (FELIX) system and passes aggregated data fragments to the High-Level Trigger (HLT) system. During Run 3, SW ROD operates in parallel with the legacy Readout System (ROS) at an input rate of 100 kHz. For the Phase-II, the legacy ROS will be completely replaced with a new system based on the next generation of FELIX and an evolution of the SW ROD application called Data Handler. Data Handler has the same functional requirements as SW ROD but must be able to operate at an input rate of 1 MHz. To facilitate this evolution the SW ROD has been implemented using plugin architecture. This contribution presents the design and implementation of the SW ROD application for Run 3, along with the strategy for its evolution to the Phase-II Readout system. It discusses the lessons learned during Run 3 and describes the challenges that have been addressed to accomplish the demanding performance requirements of HL-LHC.

Kolos, Serguei [Univ. of California, Irvine, CA (U↗
DOE OSTI2021

Design of microwave broadband CMOS transmitter and receiver circuits for MIR and ECEI plasma diagnostics

To efficiently determine the plasma electron density fluctuations using the MIR diagnostic technique, a 55–75 GHz 65 nm-CMOS transmitter has been developed where four separate intermediate frequency (IF) signals are up-converted, amplified, and then combined to generate an 8-tone RF output; a broadband 90 nm-CMOS receiver has also been constructed, which consists of an RF-low noise amplifier (LNA), mixer, and IF amplifier. The circuits and their corresponding modules will soon be deployed on the DIII-D and NSTX-U fusion devices. A 110–140 GHz 65 nm-CMOS receiver has also been designed, which is suitable for measuring the deep-core temperature fluctuations in the DIII-D tokamak using the electron cyclotron emission imaging diagnostic system. In addition to the RF-LNA/balun, mixer, and IF amplifier, an LO balun/tripler and driving amplifier are now included in this highly integrated circuit chip. By adopting the microwave and millimeterwave system-on-chip concept in the front-end system design, this paper demonstrates that compact transmitter and receiver modules can be easily built, which, in turn, facilitates array implementation and maintenance.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2023

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Quality assurance test of silicon photomultipliers and electronic boards for STAR event plane detector

The event plane detector (EPD), installed in the Solenoid Tracker at the Relativistic Heavy-Ion Collider located at the Brookhaven National Laboratory is a plastic scintillator-based device that measures the reaction centrality and event plane in the forward region of the relativistic heavy-ion collisions. We used silicon photomultiplier (SiPM) arrays to detect the photons produced in the scintillator via the fiber connection. Signals from the SiPM arrays were amplified by the front-end electronic (FEE) board, and sent to the analog-to-digital converter (ADC) boards for further processing via the receiver (RX) board. The full EPD system consisted of 24 super-sectors (SSs); each SS was equipped with two SiPM boards, two FEE boards and two RX boards, and they corresponded to 744 readout channels. All these boards were mass produced at the University of Science and Technology of China, with a dedicated quality assurance (QA) procedures applied to identify any problems before deployment. This article describes the details of the QA method and the related test system. As a result, the QA test results are presented along with the discussions.

EPD↗
DOE OSTI2025

Low-Jitter Clock Receivers for Fast Timing Applications

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

Design and Testing of the Address in Real-Time Data Driver Card for the Micromegas Detector of the ATLAS New Small Wheel Upgrade

The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data in the Micro-Mesh Gaseous Structure (Micromegas) detector of the ATLAS New Small Wheel (NSW) upgrade. The Address in Real Time (ART) signals are generated by the front-end ASIC, named VMM chip, to indicate the address of the first above-threshold event. A custom ASIC (ART ASIC) is designed to receive the ART signals from the VMM chip and implement the hit-selection. The processed data from the ART ASIC will be transmitted out of the NSW through the GBTx serializer, the unidirectional Versatile Twin Transmitter (VTTx) and fiber optical links. The ART signal is critical for the ATLAS experiment trigger selection thus the performance and stability of the ADDC is very important. To ensure extensive testing of the ADDC, an FPGA Mezzanine Card (FMC) based testing platform and a special designed firmware/software are developed. We find that this test platform works with the commercial Xilinx VC707 FPGA development kit, independent of the other electronics of the NSW it can test all the functions of the ADDC and its long-term stability. This paper will introduce the design, testing procedure and results of the ADDC and the FMC testing platform.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2023

Analysis and Compensation of Tx and Rx IQ Imbalances in Uplink IM-OFDMA Systems

Index modulation-based orthogonal division multiple access (IM-OFDMA) has recently been proposed as a potential technique for future wireless communication systems due to its superior spectral efficiency and error performance over conventional multiple access schemes. However, its performance is still under investigation by researchers in light of a variety of scenarios and assumptions. Following this direction, in this Article, the individual and joint effects of the transmitter (Tx) and receiver (Rx) in-phase and quadrature imbalances (IQI) on the bit-error-rate (BER) performance of the uplink IM-OFDMA scheme are investigated by considering whether each user's RF front-end is identical or not. Moreover, to reduce the detrimental effect of IQI, a preamble-based estimation and compensation method is proposed for IM-OFDMA. Closed-form expressions for the average BER of IM-OFDMA are obtained by considering the physical effect of the Tx and Rx IQI. Also, using Monte Carlo simulations, the derived expressions are verified under different system configurations. Furthermore, analytical and simulation results reveal that Tx and Rx IQI cause an error floor in the BER performance of IM-OFDMA schemes. However, the proposed estimation and compensation method not only reduces the impact of IQI but also leads to a better BER performance compared to the case of no IQI, which mainly refers to the frequency diversity caused by the IQI.

42 ENGINEERING↗
DOE OSTI2021

High level of integration of front-end imaging optics system for electron cyclotron emission imaging diagnostics on the DIII-D tokamak

The optics system of the Electron Cyclotron Emission Imaging (ECEI) diagnostics on the DIII-D tokamak has been developed and installed for high-resolution temperature fluctuations measurement in the previous decade. The System-on-Chip approach upgrade was finished in June 2019 with high integrated receiver array with 20 individual modules. In this paper, we design new optics with high-level integration. In the new optics system, there will be two mirrors from plasma to receiver array, including one replaceable curved mirror out of the vacuum and one fixed curved mirror in the vessel. There are two options with 1:1 and 1:2 magnifications for high poloidal resolution and larger poloidal window modes. Overall, the new optics system has multiple improvements, including lighter weight, smaller size, more flexible installation and alignment. The synthetic ECEI module is used to evaluate the new optics system.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2023

CMS High Granularity Calorimeter ECON-D ASIC overview and radiation testing results

The Compact Muon Solenoid (CMS) Experiment’s High Granularity Calorimeter (HGCAL) upgrade replaces the CMS electromagnetic and hadronic endcap calorimeters in preparation for the high-rate and high-radiation environment of the High Luminosity LHC. To effectively use the over 6 million channels of this highly-segmented “imaging” calorimeter, CMS is pioneering very front-end data compression with the Endcap Concentrator (ECON) ASICs – the ECON-T for the trigger path and the ECON-D for the data path. These 65 nm CMOS ASICs are radiation tolerant (200 Mrad) and low-power (< 2.5 mW/channel). In June 2023, we received the first full-functionality prototype of the data path concentrator ASIC, the ECON-D-P1. This talk will present an overview of the ECON-D-P1, summarize functionality and system testing, and present results from both Total Ionizing Dose (TID) and Single Event Effect (SEE) testing campaigns completed in summer 2023, validating the ECON-D radiation tolerant performance.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

High-bandwidth reconfigurable data acquisition card

A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.

Chen, Kai↗
DOE OSTI2023

Social Acceptance of a Reduced-Footprint Synthetic Mooring System for Floating Offshore Wind Turbines in the Gulf of Maine

Engineers are looking to reduce the size of floating offshore wind mooring footprints to minimize conflict with other ocean users. To this end, the University of Maine (UMaine) received funding from the United States Department of Energy (DOE) to design, demonstrate, and validate a novel reduced-footprint synthetic mooring system for floating offshore wind turbines (FOWTs) that reduces impacts to fisheries and the levelized cost of energy. UMaine designed two mooring systems for the New England Aqua Ventus (NEAV) I demonstration project to quantify the technical, economic, and social impacts of a reduced-footprint hybrid mooring system. Specifically, a traditional catenary chain mooring system and a novel polyester rope-chain hybrid system were designed to the front-end engineering design level for this assessment. The National Renewable Energy Laboratory (NREL) was funded by DOE to help independently quantify the social and techno-economic impacts of the rope-chain hybrid mooring system designed by UMaine. This report focuses on NREL's assessment of the social acceptance of the reduced-footprint rope-chain hybrid mooring system and the conventional all-chain mooring system by competing users in the Gulf of Maine.

ENGINEERING,WIND ENERGY↗
DOE OSTI2020

Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

QTIA, a 2.5 or 10 Gbps 4-channel array optical receiver ASIC in a 65 nm CMOS technology

Here, the Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Production and tests of the ADDC for the Micromegas detector of the ATLAS New Small Wheel

The Large Hadron Collider (LHC) at CERN will perform a series of upgrades to allow luminosity increases during the next physics runs expected from 2022 on. These will also significantly increase the trigger rates of all the detectors. As part of the ATLAS Phase-I upgrade, the current Small Wheel muon detectors will be replaced with state-of-the-art New Small Wheel (NSW) detectors to cope with the increased luminosity of the LHC. The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data from the resistive Micro-Mesh Gaseous Structure (Micromegas) detectors of the NSW. The ART ASIC on the ADDC is a customdesigned chip to receive theAddress in Real Time (ART) signals from theVMMfront-end ASIC and perform hit-selection processing. The processed trigger data is then sent to the Trigger Processor (TP) through optical links. A total of 512 ADDCs will be installed on the detector close to the front-end boards. Therefore, those cards must be able to work properly in a high radiation and magnetic field environment. Furthermore, after four rounds of prototyping, the ADDC production was launched in January of 2019. 600 ADDC boards have been produced and tested with an automated test stand. This test setup can simulate the front-end signals and provide "Level-1 Data Driver Card" (L1DDC) functions as well as part of the TP functions. Thus, the ADDC functionality and stability can be verified without the remaining NSW electronics. This paper describes the ADDC hardware prototype development, radiation and integration testing, and the ADDC automated production test procedure.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

Method and apparatus for front end gather/scatter memory coalescing

A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.

97 MATHEMATICS AND COMPUTING↗