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Radiation hardening technologies for electronics are the conventional approach for survivability in high radiation environments. This paper presents a novel approach based on evolvable hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged compoenents.
Reconfigurable or programmable photonic devices are rapidly growing and have become an integral part of many optical systems. The ability to selectively modulate electromagnetic waves through electrical stimuli is crucial in the advancement of a variety of applications from data communication and computing devices to environmental science and space explorations. Chalcogenide-based phase change materials (PCMs) are one of the most promising material candidates for reconfigurable photonics due to their large optical contrast between their different solid-state structural phases. Although significant efforts have been devoted to accurate simulation of PCM-based devices, in this paper, we highlight three important aspects which have often evaded prior models yet having significant impacts on the thermal and phase transition behavior of these devices: the enthalpy of fusion, the heat capacity change upon glass transition, as well as the thermal conductivity of liquid-phase PCMs. We further investigated the important topic of switching energy scaling in PCM devices, which also helps explain why the three above-mentioned effects have long been overlooked in electronic PCM memories but only become important in photonics. Our findings offer insight to facilitate accurate modeling of PCM-based photonic devices and can inform the development of more efficient reconfigurable optics.
Origami offers a distinct approach for designing and engineering new material structures and properties. The folding and stacking of atomically thin van der Waals (vdW) materials, for example, can lead to intriguing new physical properties including bandgap tuning, Van Hove singularity, and superconductivity. On the other hand, achieving well-controlled folding of vdW materials with high spatial precision has been extremely challenging and difficult to scale toward large areas. In this paper, a deterministic technique is reported to fold vdW materials at a defined position and direction using microfluidic forces. Electron beam lithography (EBL) is utilized to define the folding area, which allows precise control of the folding geometry, direction, and position beyond 100 nm resolution. Using this technique, single-atomic-layer vdW materials or their heterostructures can be folded without the need for any external supporting layers in the final folded structure. In addition, arrays of patterns can be folded across a large area using this technique and electronic devices that can reconfigure device functionalities through folding are also demonstrated. Such scalable formation of folded vdW material structures with high precision can lead to the creation of new atomic-scale materials and superlattices as well as opening the door to realizing foldable and reconfigurable electronics.
Chalcogenide Phase Change Materials (PCM) and metal insulator transition (MIT) materials are a group of materials that are capable of switching between low resistance and high resistance states. These emerging materials have been widely used in optical storage media and memory devices. Over the past recent years, there have been interests in exploiting the PCM and MIT materials, especially germanium antimony telluride (GST) alloys and vanadium dioxide (VO 2 ), for radio frequency (RF) applications. The PCM and MIT-based RF devices are expected to bridge the gap between semiconductor switches and microelectromechanical system (MEMS) switches as they combine the low insertion loss performance of MEMS technology and the small size and reliability performance of semiconductor technology. This article presents an overview of the PCM and MIT materials for RF circuits and discusses the recent advancements in reconfigurable millimeter-wave (mmWave) devices based on PCM and MIT materials in depth.
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A system includes an input device having first and second input members configured to be activated by a user. The input device is configured to generate activation signals associated with activation of the first and second input members, and each of the first and second input members are associated with an input function. A processor is coupled to the input device and configured to receive the activation signals. A memory coupled to the processor, and includes a reconfiguration module configured to store the input functions assigned to the first and second input members and, upon execution of the processor, to reconfigure the input functions assigned to the input members when the first input member is inoperable.
The paper presents and compares two approaches to design fault-tolerant evolvable hardware: one based on the fitness definition and the other based on the population statistics.
Significance Colloidal nanocrystals with defined sizes and shapes are ideal building blocks for nanofabrication. However, the ability to arbitrarily arrange them on surfaces with control over their orientation remains elusive. Here we report a shallow-template-assisted DNA-mediated assembly strategy to precisely arrange colloidal nanocrystals on surfaces, with single-particle control across submillimeter areas. In addition, the oligonucleotide bonds between the nanocrystals and substrate can be reversibly expanded and contracted enabling postsynthetic tunability of the assembled structures. Using this approach, we synthesized a nanocrystal-based, dynamically tunable metasurface (an anomalous reflector), thereby illustrating the potential for unique device construction via DNA programmable assembly.
Reconfigurable devices offer the ability to program electronic circuits on demand. Here, in this work, we demonstrated on-demand creation of artificial neurons, synapses, and memory capacitors in post-fabricated perovskite NdNiO 3 devices that can be simply reconfigured for a specific purpose by single-shot electric pulses. The sensitivity of electronic properties of perovskite nickelates to the local distribution of hydrogen ions enabled these results. With experimental data from our memory capacitors, simulation results of a reservoir computing framework showed excellent performance for tasks such as digit recognition and classification of electrocardiogram heartbeat activity. Using our reconfigurable artificial neurons and synapses, simulated dynamic networks outperformed static networks for incremental learning scenarios. The ability to fashion the building blocks of brain-inspired computers on demand opens up new directions in adaptive networks.
Space missions often require radiation and extreme-temperature hardened electronics to survive the harsh environments beyond Earth's atmosphere. Traditional approaches to preserve electronics incorporate shielding, insulation and redundancy at the expense of power and weight. However, a novel way of bypassing these problems is the concept of evolutionary hardware. A reconfigurable device, consisting of several switches interconnected with analog/digital parts, is controlled by an evolutionary processor (EP). When the EP detects degradation in the circuit it sends signals to reconfigure the switches, thus forming a new circuit with the desired output. This concept has been developed since the mid-l990s, but one problem remains-the EP cannot degrade substantially. For this reason, extensive testing at extreme temperatures (-180 to 120 C) has been done on devices found on FPGA boards (taking the role of the EP), such as the Analog to Digital and the Digital to Analog Converter. The EP is used in conjunction with a bias-controlled amplifier and a new prototype relay board, which is interconnected with 6 G4-FETs, a tri-input transistor-like element developed at JPL. The greatest improvements to be made lie in the reconfigurable device, so future design and testing of the G4-FET chip is required.
This paper presents JPL progress in building evolution-oriented reconfigurable devices.
This paper serves a twofold purpose: characterize the behavior of a reconfigurable chip exposed to radiation; and demonstrate a method for functionality recovery due to Total Ionizing Dose (TID) effects. The experiments are performed using a PL developed reconfigurable device, a Field Programmable Transistor Array (FPTA). The paper initially describes experiments on the characterization of the NMOS transistor behavior for TID values up to 300krad. The behavior of analog and digital circuits downloaded onto the FPTA chip is also assessed for TID effects. This paper also presents a novel approach for circuit functionality recovery due to radiation effects based on Evolvable Hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. Experiments with total radiation dose up to 300kRad show that while the functionality of a variety of circuits, including digital gates, a rectifier and a Digital to Analog Converter implemented on a FPTA-2 chip is degraded/lost at levels before 200kRad, the correct functionality can be recovered through the proposed evolutionary approach and the chips are able to survive higher radiation, for several functions in excess of total radiation dose of 250kRad.
This paper argues in favor of adaptive reconfiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. Laboratory demonstrations of this technique were performed by JPL in several independent experiments in which bulk CMOS reconfgurable devices were exposed to, and degraded by, high temperatures (approx.300 C) or radiation (300kRad TID), and then recovered by adaptive reconfiguration using evolutionary search algorithms.
A stackable form-factor Peripheral Component Interconnect (PCI) device can be configured as a host controller or a master/target for use on a PCI assembly. PCI device may comprise a multiple-input switch coupled to a PCI bus, a multiplexor coupled to the switch, and a reconfigurable device coupled to one of the switch and multiplexor. The PCI device is configured to support functionality from power-up, and either control function or add-in card function.
Two-dimensional (2D) semiconductor heterostructures are key building blocks for many electronic and optoelectronic devices. Reconfiguring the band-edge states and modulating their interplay with charge carriers at the interface in a continuous manner have long been sought yet are challenging. Here, using organic semiconductor–incorporated 2D halide perovskites as the model system, we realize the manipulation of band-edge states and charge distribution via mechanical—rather than chemical or thermal—regulation. Compression induces band-alignment switching and charge redistribution due to the different pressure responses of organic and inorganic building blocks, giving controllable emission properties of 2D perovskites. We propose and demonstrate a “pressure gating” strategy that enables the control of multiple emission states within a single material. We also reveal that band-alignment transition at the organic-inorganic interface is intrinsically not well resolved at room temperature owing to the thermally activated transfer and shuffling of band-edge carriers. This work provides important fundamental insights into the energetics and carrier dynamics of hybrid semiconductor heterostructures.
The Software Defined Architectures (SODA) Synthesizer is an open-source compiler-based tool able to automatically generate domain-specialized systems targeting Application-Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) starting from high-level programming. SODA is composed of a frontend, SODA-OPT, which leverages the multilevel intermediate representation (MLIR) framework to interface with productive programming tools (e.g., machine learning frame-works), identify kernels suitable for acceleration, and perform high-level optimizations, and of a state-of-the-art high-level synthesis backend, Bambu from the PandA framework, to generate custom accelerators. One specific application of the SODA Synthesizer is the generation of accelerators to enable ultra-low latency inference and control on autonomous systems for scientific discovery (e.g., electron microscopes, sensors in particle accelerators, etc.). This paper provides an overview of the flow in the context of the generation of accelerators for edge processing to be integrated in transmission electron microscopy (TEM) devices, focusing on use cases from precision material synthesis. We show the tool in action with an example of design space exploration for inference on reconfigurable devices with a conventional deep neural network model (LeNet). Finally, we discuss the research directions and opportunities enabled by SODA in the area of autonomous control for scientific experimental workflows.
Coarse-grained reconfigurable arrays (CGRAs),loosely defined as arrays of functional units (e.g, adder, sub-tractor, multiplier, divider, or larger multi-operation units, butsmaller than a general-purpose core) interconnected through aNetwork-on-Chip, provide higher flexibility than domain-specificASIC accelerators while offering increased hardware efficiencywith respect to fine-grained reconfigurable devices, such as FieldProgrammable Gate Arrays (FPGAs). The fast evolving fieldsof machine learning and edge computing, which are seeing acontinuous flow of novel algorithms and larger models, makeCGRAs ideal target architectures to allow domain specializationwithout loosing too much generality. They also generally offerquicker and more effective reconfigurability than FPGAs, po-tentially allowing adaptation during actual algorithm execution,and implement a dataflow programming paradigm that adaptswell to these emerging workloads. Designing and generating aCGRA, however, still requires to define the type and number ofthe specific functional units, implement their interconnect andthe network topology, and perform its simulation and validation,given a variety of workloads of interest.In this paper, we propose OpenCGRA, a Python-based unifiedframework that integrates generation, modeling, testing and eval-uation for CGRAs. OpenCGRA is the first open-source integratedframework able to support the full top-to-bottom design flow forspecializing and implementing CGRAs: modeling at different ab-straction levels (functional level, cycle level, register-transfer level),generation, simulation, testing at different granularities (unit test-ing, integration testing, property-based testing), and characteriza-tion (area, power, and timing). OpenCGRAs will be made availableon GitHub.
Coarse-grained reconfigurable arrays (CGRAs), loosely defined as arrays of functional units interconnected through a network-on-chip (NoC), provide higher flexibility than domain-specific ASIC accelerators while offering increased hardware efficiency with respect to fine-grained reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs). Un-fortunately, designing a CGRA for a specific application domain involves enormous software/hardware engineering effort (e.g., designing the CGRA, map operations onto the CGRA, etc) and requires the exploration on a large design space (e.g., applying appropriate loop transformation on each application, specializing the reconfigurable processing elements of the CGRA, refining the network topology, deciding the size of the data memory, etc). Int his paper, we propose AURORA – a software/hardware co-design framework to automatically synthesize optimal CGRA given a set of applications of interest