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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records

Gated ring oscillator with constant dynamic power consumption

A pure digital ring oscillator with constant power consumption as oscillation frequency is adjusted. Circuit topology includes a multiplexer implemented in NAND gates and a delay element positioned after a path selection NAND gate of that multiplexer such that delay element transistors may not toggle if the non-delaying signal path is selected. Assuming a delay element oscillation frequency f and a total capacitance C, and also assuming a plurality N of delay gates each characterized by a propagation delay t1 and a capacitance C1 such that C=C1*N, the ring oscillator of the present invention is characterized by a C value that is proportional to N and an f value that is inversely proportional to N. Furthermore, each of the N delay gates as well as the input and output gates of the multiplexer are characterized by a common capacitance-to-propagation delay ratio=C1/t1.

Wu, Jinyuan↗

Gated ring oscillator with constant dynamic power consumption

A pure digital ring oscillator with constant power consumption as oscillation frequency is adjusted. Circuit topology includes a multiplexer implemented in NAND gates and a delay element positioned after a path selection NAND gate of that multiplexer such that delay element transistors may not toggle if the non-delaying signal path is selected. Assuming a delay element oscillation frequency f and a total capacitance C, and also assuming a plurality N of delay gates each characterized by a propagation delay t1 and a capacitance C1 such that C=C1*N, the ring oscillator of the present invention is characterized by a C value that is proportional to N and an f value that is inversely proportional to N. Furthermore, each of the N delay gates as well as the input and output gates of the multiplexer are characterized by a common capacitance-to-propagation delay ratio=C1/t1.

Wu, Jinyuan↗

Characterization of Noise in CMOS Ring Oscillators at Cryogenic Temperatures

Allan deviation provides a means to characterize the time-dependence of noise in oscillators and potentially identify the source characteristics. Measurements on a 130 nm, 7-stage ring oscillator show that the Allan deviation declines from 300 K to 150 K as expected, but surprisingly increases from 150 K to 11 K. At low temperatures, the measured Allan deviation can be well fit using a few random telegraph noise (RTN) sources over the range of a few kilohertz to a few gigahertz. Further, the RTN characteristics evolve to reveal an enhanced role in low-frequency noise at lower temperatures.

47 OTHER INSTRUMENTATION↗

A buckling-sheet ring oscillator for electronics-free, multimodal locomotion

Locomotion of soft robots typically relies on control of multiple inflatable actuators by electronic computers and hard valves. Soft pneumatic oscillators can reduce the demand on controllers by generating complex movements required for locomotion from a single, constant input pressure, but either have been constrained to low rates of flow of air or have required complex fabrication processes. Here, we describe a pneumatic oscillator fabricated from flexible, but inextensible, sheets that provides high rates of airflow for practical locomotion by combining three instabilities: out-of-plane buckling of the sheets, kinking of tubing attached to the sheets, and a system-level instability resulting from connection of an odd number of pneumatic inverters made from these sheets in a loop. This device, which we call a “buckling-sheet ring oscillator” (BRO), directly generates movement from its own interaction with its surroundings and consists only of readily available materials assembled in a simple process—specifically, stacking acetate sheets, nylon film, and double-sided tape, and attaching an elastomeric tube. A device incorporating a BRO is capable of both translational and rotational motion over varied terrain (even without a tether) and can climb upward against gravity and downward against the buoyant force encountered under water.

Robotics↗

Novel Cascaded Ring Oscillator Vernier based TDC Architecture with a Feedthrough Reference Oscillator

Time to digital converters (TDCs) are widely used in particle physics and medical imaging to determine the relative arrival time of photons and other particles. Vernier TDCs are one of the most attractive options due to their power consumption efficiency and their small footprint. We present our newly patented innovative architecture of cascaded-stage Vernier TDCs comprised of a feedthrough reference oscillator. This architecture lead to successive Vernier measurements that result in a lower number of cycles for the same dynamic range to resolution ratio (DRRR), leading to reduced conversion time and lower jitter. To validate this architecture, a test chip was designed in 0.18~μm TSMC technology, integrating four types of cascaded Vernier TDCs with an increasing number of stages. The performance of the chip was assessed using a modular test platform specifically designed for TDCs. For comparison purposes, all TDCs were tested with a LSB of 50~ps and a dynamic range of 20~ns. The experimental results demonstrate the highest gain in performance between 1 stage Vernier and 2 stage Vernier TDCs with the precision improved from 36~ps~rms to 21~ps~rms, the maximum number of turns from 110 to 25 counts and the dead time, from 266.4~ns to 76.5~ns, on average. Adding Vernier stages is only relevant for a higher DRRR. Therefore, the 3-stage and 4-stage Vernier TDCs also show performance gains, but improvements are limited.

Scarpellini, Robin↗

Comparison of Hafnium Dioxide and Zirconium Dioxide Grown by Plasma-Enhanced Atomic Layer Deposition for the Application of Electronic Materials

We report the growth of nanoscale hafnium dioxide (HfO 2 ) and zirconium dioxide (ZrO 2 ) thin films using remote plasma-enhanced atomic layer deposition (PE-ALD), and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using the HfO 2 and ZrO 2 thin films as the gate oxide. Tetrakis (dimethylamino) hafnium (Hf[N(CH 3 ) 2 ] 4 ) and tetrakis (dimethylamino) zirconium (IV) (Zr[N(CH 3 ) 2 ] 4 ) were used as the precursors, while O 2 gas was used as the reactive gas. The PE-ALD-grown HfO 2 and ZrO 2 thin films were analyzed using X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), and high-resolution transmission electron microscopy (HRTEM). The XPS measurements show that the ZrO 2 film has the atomic concentrations of 34% Zr, 2% C, and 64% O while the HfO 2 film has the atomic concentrations of 29% Hf, 11% C, and 60% O. The HRTEM and XRD measurements show both HfO 2 and ZrO 2 films have polycrystalline structures. n-channel and p-channel metal-oxide semiconductor field-effect transistors (nFETs and pFETs), CMOS inverters, and CMOS ring oscillators were fabricated to test the quality of the HfO 2 and ZrO 2 thin films as the gate oxide. Current-voltage (IV) curves, transfer characteristics, and oscillation waveforms were measured from the fabricated transistors, inverters, and oscillators, respectively. The experimental results measured from the HfO 2 and ZrO 2 thin films were compared.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

Design of Hopfield Networks Based on Superconducting Coupled Oscillators

The global energy shortage has driven the development of many energy-efficient computational platforms beyond Moore's law, among which brain-inspired neuromorphic computing is one of the promising solutions. Associative memory and pattern recognition are important computations solved by brain-inspired Hopfield networks. Classical Hopfield networks store memories via fixed point attractors of their dynamics. In oscillatory Hopfield networks, these attractors are replaced by periodic orbits. Here, we design an oscillatory Hopfield network based on coupled superconducting oscillators. We first employ a mathematical phase reduction approach to map networks of coupled superconducting rapid single flux quantum (RSFQ) ring oscillators to coupled Kuramoto phase-oscillator networks. We use this theory to numerically optimize the hardware's mutual inductances in order to directly match the phase-reduced superconducting oscillators to a model of phase-oscillator-based Hopfield networks. The resulting network can store multiple oscillatory phase-locked memory patterns and recover the patterns based on the initial phase conditions. As different pattern recognition tasks, or learning, require tunable connectivity strengths between the oscillatory nodes, we further employ a coupler circuit that enables tuning the coupling strength between two oscillators by applying an external flux. We demonstrate the functionality of our design through numerical simulations of a small example network with oscillators operating at 86 GHz and recognizing patterns within 10 ns. Our approach enables the learning and retrieval of dynamical memory patterns with a wide range of applications where rhythmic dynamic output is beneficial.

Cheng, Ran↗

Coherent ring-current migration of Mg-phthalocyanine probed by time-resolved X-ray circular dichroism

The coherent ring current of Mg-phthalocyanine created by a broad band UV-visible pump pulse shows variation with time, where the ring currents at the corner benzene rings, around the Mg cation and on the outer ring oscillate with different time periods and the current density migrates among these regions. The 7 pairs of E u degenerate excited states populated upon photoexcitation, generate 21 distinct coherent ring currents. We further calculate the time-resolved X-ray circular dichroism (TRXCD) spectrum of the coherences contributing to the ring current obtained by an attosecond X-ray probe pulse resonant with the nitrogen K-edge. A frequency domain TRXCD signal obtained by a Fourier transform of the signal with respect to the pump-probe delay time clearly separates the currents induced by different state pairs.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

The low frequency edge oscillation in alcator C-Mod and ASDEX upgrade I-mode

The low frequency edge oscillation (LFEO) is a low frequency fluctuation in many plasma quantities in the pedestal region of the I-Mode confinement regime. It is observed on Alcator C-Mod between 10–30 kHz and on ASDEX Upgrade between 5–10 kHz. On both tokamaks it has been previously identified as a geodesic acoustic mode (GAM), however the recent discovery of the edge temperature ring oscillation (ETRO) in a similar frequency and spatial location as the LFEO in I-Modes on EAST has called this identification into question. In this paper we investigate the LFEO on C-Mod and AUG using a variety of different experimental techniques including spectral analysis, magnetic mode number analysis, localization, and direct measurement of the LFEO zonal structure and propagation using a mirror Langmuir probe. This investigation has reconfirmed the identification of the LFEO as a GAM and determined that it has several key differences from the ETRO.

AUG↗

An Analysis of FPGA LUT Bias and Entropy for Physical Unclonable Functions

Process variations within Field Programmable Gate Arrays (FPGAs) provide a rich source of entropy and are therefore well-suited for the implementation of Physical Unclonable Functions (PUFs). However, careful considerations must be given to the design of the PUF architecture as a means of avoiding undesirable localized bias effects that adversely impact randomness, an important statistical quality characteristic of a PUF. Here in this paper, we investigate a ring-oscillator (RO) PUF that leverages localized entropy from individual look-up table (LUT) primitives. A novel RO construction is presented that enables the individual paths through the LUT primitive to be measured and isolated at high precision, and an analysis is presented that demonstrates significant levels of localized design bias. The analysis demonstrates that delay-based PUFs that utilize LUTs as a source of entropy should avoid using FPGA primitives that are localized to specific regions of the FPGA, and instead, a more robust PUF architecture can be constructed by distributing path delay components over a wider region of the FPGA fabric. Compact RO PUF architectures that utilize multiple configurations within a small group of LUTs are particularly susceptible to these types of design-level bias effects. The analysis is carried out on data collected from a set of identically designed, hard macro instantiations of the RO implemented on 30 copies of a Zynq 7010 SoC.

97 MATHEMATICS AND COMPUTING↗

A sub-5 ps jitter time-to-digital converter ASIC with back-gate delay tuning in 22 nm CMOS

We present the design of a Time-to-Digital Converter (TDC) ASIC together with performance characterization results at cryogenic temperature (6-8 K), and at room temperature using emulated Low-Gain Avalanche Detector (LGAD) signals. The TDC design uses a two-step architecture with a ring-oscillator based counter and a Vernier delay line fine TDC. The TDC is implemented in an FD-SOI process, and back-gate tuning is used not only to correct threshold variation due to cryogenic operation, but also as a novel way to tune TDC delay elements with very little overhead. Using this technique, we demonstrate a design with very low power (0.5 mW) and area (0.003 mm 2 ). We present test results using the Fermilab Constant Fraction Discriminator (FCFD) ASIC to produce discriminated signals from an internal charge injection mechanism that mimics the waveform and signal amplitude of minimum ionizing particles impinging on LGAD sensors. We characterize the time precision of the full system and verify that the TDC ASIC contributes a negligible amount to the total system time precision, fully consistent with the expected jitter contribution of less than 5 ps. In conclusion, the results presented here demonstrate the utility of our TDC for applications in physics and quantum communications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Strain-insensitive intrinsically stretchable transistors and circuits

An all-elastomer strain engineering approach, which uses patterned elastomer layers with tunable stiffnesses, can be used to create intrinsically stretchable transistor arrays with a device density of 340 transistors cm -2 and strain insensitivity of less than 5% performance variation when stretched to 100% strain. Intrinsically stretchable electronics can form intimate interfaces with the human body, creating devices that could be used to monitor physiological signals without constraining movement. However, mechanical strain invariably leads to the degradation of the electronic properties of the devices. Here we show that strain-insensitive intrinsically stretchable transistor arrays can be created using an all-elastomer strain engineering approach, in which the patterned elastomer layers with tunable stiffnesses are incorporated into the transistor structure. By varying the cross-linking density of the elastomers, areas of increased local stiffness are introduced, reducing strain on the active regions of the devices. This approach can be readily incorporated into existing fabrication processes, and we use it to create arrays with a device density of 340 transistors cm -2 and a strain insensitivity of less than 5% performance variation when stretched to 100% strain. We also show that it can be used to fabricate strain-insensitive circuit elements, including NOR gates, ring oscillators and high-gain amplifiers for the stable monitoring of electrophysiological signals.

42 ENGINEERING↗

Impacts of Substrate Thinning on FPGA Performance and Reliability [Slides]

Substrate thinning is necessary in devices with flip-chip BGA packages to enable both radiation testing and component qualification and high-spatial resolution beam-based failure analysis methods. We investigated three factors affecting device performance: subsurface damage from the thinning process, reduced heat spreading in thin substrates, and changes in device switching speed. We conclude subsurface damage to crystalline Si caused by the thinning process is removable with sufficient SiO 2 slurry polishing. Local temperature differences increase minimally in devices thinned to 3 μm. Compressive stress in the Si increases globally after device thinning and leads to slowing of ring oscillator frequency by about 0.5% compared to full-thickness devices. Future work will include extending the results to submicron Si thickness values, which also has important benefits for failure analysis, debug, and security assessments. We also plan to extend this type of work to other FPGAs and other devices like memory and processors.

36 MATERIALS SCIENCE↗

Radiation-Hardened GaN HEMT and Cell Design, Modeling, and Fabrication for Nuclear Instrumentation Applications

Recent advances in nuclear power generation technologies show great promise for efficient, safe generation of carbon-free power in the near future. Consequently, many new generation reactor designs are being pursued by government and industry groups, including both fission- and fusion-based technologies. Radiation- and temperature-tolerant sensor technology continues to advance, yet development of the electronics/instrumentation technologies suitable for these environments have fallen behind. Industry has adequately addressed harsh environment electronics needs for low earth orbit satellites, but the much more extreme conditions associated with electronics placed near or in a reactor core remain unaddressed. This project investigates the use of gallium nitride (GaN) circuit technology to address the unique needs for sensor interface electronics and communications in reactor environments. This report provides a summary of the first year’s project activities related to developing and optimizing devices and circuits for this GaN high electronic mobility transistor (HEMT) process. Activities reported include multiple analog and digital circuit designs simulated using custom Verilog-A models generated from measured GaN devices fabricated in the target process. Digital circuit designs included fundamental logic circuits such as an inverter, NAND, NOR, AND and OR gates, as well as a 5-stage ring oscillator. Each design was simulated using an open-source SPICE simulator, and an integrated circuit layout was produced of each design for use in future fabrication. Analog circuit designs focused on the fundamental building blocks to be used to construct sensor interface and communications circuits. These included current mirrors, matched differential pairs, and a Gilbert cell mixer design, each with an associated integrated circuit layout. Layout tools used for these designs included two open-source packages—KLayout and Magic—which were customized for specific use with the OSU GaN process layers. Design rules and preliminary device extraction capabilities were built for the Magic tool to enable device extraction and subsequent netlist generation for SPICE simulation. Finally, future research directions for year two are summarized. When the year-two directions are implemented, the project will be in position to advance the state of the art in electronics for near- or in-reactor sensor interfacing and communications.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

60 Co γ Irradiation of a CMS CROC v2 to 1.6 Grad

This paper reports the irradiation of the production version of the readout chip for the CMS HL-LHC pixel detector, CROC~v2, to 1.6~Grad using γ s from a 60 Co source at Sandia National Laboratory. The CROC~v2 was kept powered, configured, and maintained as close as possible to its nominal operating temperature of -20~ o C during irradiation. Internal chip voltages, pixel response, and diagnostic ring oscillators were continuously monitored, and thresholds were optimized frequently. The CROC~v2 performed according to specifications at 1.6~Grad. Where available, these results will be compared with those for this and earlier iterations of the RD53 readout chip irradiated to a few Grad with lower-energy X-ray sources.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

Monolithic Integration of Lateral HV Power MOSFET with LV CMOS for SiC Power IC Technology

This paper reports the design and process flow for monolithic integration of lateral high voltage (HV) power MOSFET with low voltage (LV) CMOS circuits for SiC Power IC technology. The reported devices and circuits are fabricated on a N-/N+ 4H-SiC substrate at 150mm, production grade- Analog Devices Inc. (ADI) Hillview fabrication facility located in San Jose. Here, the static performance characteristics of HV NMOS and LV CMOS are reported. For future high temperature applications, the static performances are fully characterized and are reported up to 200oC. Finally, to validate the fabricated CMOS, a 5-stage ring oscillator is also demonstrated.

4H-SiC↗

Manipulation of the Magnetoresistance by Strain in Topological TaSe 3

1D TaSe 3 exhibits many unusual physical properties due to its distorted type-II chains. Ribbon-shaped single crystals can be easily bended along the $b-axis$, forming rings. This study investigates the magnetoresistance (MR) of TaSe 3 up to 60 T in both unbended (ribbon shape) and ring-shaped (bended ribbon) samples. Notable changes are found in the magnetotransport properties between the two different shaped samples. One is that the MR in ring-shaped samples is three orders lower than that in unbended samples under the same sample environment. In addition, linear MR is observed above ≈20 T in ring-shaped samples when the magnetic field is parallel or perpendicular to the rings. Quantum oscillations are also observed as a function of the magnetic field when the magnetic field is applied parallel to rings, possibly due to the Altshuler–Aronov–Spivak effect or the inversion of the lowest Landau level beyond the quantum limit. All these results are related to strain-induced electronic structure change in TaSe 3 , an effective way to tune physical properties in low-dimensional materials.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗