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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Graphene-Based Quantum Hall Interferometer with Self-Aligned Side Gates

The vanishing band gap of graphene has long presented challenges for fabricating high-quality quantum point contacts (QPCs)–the partially transparent p-n interfaces introduced by conventional split-gates tend to short the QPC. This complication has hindered the fabrication of graphene quantum Hall Fabry-P'erot interferometers, until recent advances have allowed split-gate QPCs to operate utilizing the highly resistive ν = 0 state. Here, we present a simple recipe to fabricate QPCs by etching a narrow trench in the graphene sheet to separate the conducting channel from self-aligned graphene side gates. Finally, we demonstrate operation of the individual QPCs in the quantum Hall regime, and further utilize these QPCs to create and study a quantum Hall interferometer.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS2019

Performance Evaluation of High-Speed, Low-Side Gate Driver, FAN3122, over Extended Temperature Range

Emerging power metal-oxide semiconductor field-effect transistor (MOSFETs) based on silicon carbide and gallium nitride technology are finding widespread use in many electronic applications such as motor control and DC/DC converters due to their higher voltage, higher temperature tolerance, and higher frequency switching capabilities. To utilize these power devices and to meet circuit/system compactness, modularity, and operational functionality, gate drivers that provide unique attributes, such as fast switching and high-current handling capability, are needed. In addition, power systems geared for use in space mission applications require on-board devices to withstand exposure to extreme temperatures and wide thermal swings. Very little data, however, exist on the performance of such devices and circuits under extreme temperatures. In this work, the performance of a high-speed gate driver with potential use in controlling power-level transistors was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance for potential use of this device in space exploration missions under extreme temperature conditions.

Wide Bandgap Semiconductors↗
DOE OSTI2025

Packaging a 650V/400A GaN Half-bridge Power Module with Ultra-low Parasitics for Electric Vehicle Drive Applications

This paper proposes a compact and efficient half-bridge power module with three 650 V / 150 A GaN dies in parallel. The power module incorporates a main power printed circuit board (PCB), an interface PCB, and a flex PCB to achieve low parasitics in both power loop and gate-side connection, resolving the issue of high parasitics typically encountered with wire bonding in high-current applications. Additionally, the interface PCB decouples the design constraints between the power loop and the gate loops. The proposed design is optimized with a vertical loop configuration to reduce power loop inductance through magnetic flux cancellation. Finite element analysis indicates that the power loop inductance is 0.58 nH at 100 MHz, while the maximum die junction temperature reaches 131 °C under an ambient temperature of 65 °C and a load current of 385 A. The proposed multi-piece PCB structure reduces the inductance of the drive circuit to minimize EMI and to mitigate false triggering. At the same time, it reduces impedance mismatches across different driver circuits, thereby achieving dynamic current sharing in multi-chip parallel configurations. Under simulation conditions of 400 V / 385 A, the current imbalance among chips was limited to 5 A. A 400 V / 385 A double-pulse test was conducted to experimentally validate the performance of the proposed power module.

30 DIRECT ENERGY CONVERSION↗
NASA NTRS2001

Simulations of Resonant Intraband and Interband Tunneling Spin Filters

This viewgraph presentation reviews resonant intraband and interband tunneling spin filters It explores the possibility of building a zero-magnetic-field spin polarizer using nonmagnetic III-V semiconductor heterostructures. It reviews the extensive simulations of quantum transport in asymmetric InAs/GaSb/AlSb resonant tunneling structures with Rashba spin splitting and proposes a. new device concept: side-gated asymmetric Resonant Interband Tunneling Diode (a-RITD).

resonant tunneling↗
NASA NTRS2008

Efficient G(sup 4)FET-Based Logic Circuits

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Vatan, Farrokh↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
DOE OSTI2025

Integration Methods for High-Density Integrated Electric Drives (Final Technical Report)

The project goal was to research, design and fabricate high-power-density, high-performance SiC power electronic modules for motor drive inverters in electric vehicles (EVs) to enable the subsequent motor drive to achieve a power density of 100 kW/l. EVs use electric motors instead of internal combustion engines as the prime mover, and their core components are semiconductor-based power electronic modules. Efficient power electronic modules play a vital role in power conversion systems. The performance of power modules directly affects the energy efficiency and overall performance of electric vehicles. Therefore, it is particularly important to develop power modules with high power density and high electrical performance that will perform reliably under EV environmental conditions. To achieve these goals, advanced electronic packaging technologies are required. This report describes a 5-year effort to integrate key aspects surrounding the basic power devices into the module itself to increase power density. These include sensing and sensing readout circuits, gate driver circuits, and two-sided cooling solutions.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2025

Defect-engineered GaN high electron mobility transistors for enhanced radiation tolerance

This study explores the radiation resilience of GaN high-electron-mobility transistors (HEMTs) under various preconditioning treatments—pristine, electro-pulsed, electrically overstressed, and 60 Co gamma-irradiated—with a focus on enhancing survivability in high-radiation environments. Key findings emphasize the gate region’s central role in radiation sensitivity, with increased defect concentrations leading to reduced sensitivity—as determined from reduced single-event transient intensities during pulsed-laser studies—and impacting charge-transport dynamics. Notably, the most sensitive region shifted as a function of bias state, with the drain side of the gate being most sensitive under negative gate bias and the source side under unbiased conditions due to two-dimensional electron gas disruptions. These insights clarify the mechanisms influencing radiation sensitivity in microelectronics and highlight the potential of defect and strain engineering to enhance the radiation hardness of GaN HEMTs across various operational states, providing valuable guidance for applications in space, defense, and other radiation-rich environments.

36 MATERIALS SCIENCE↗
NASA NTRS1974

Apparatus for inserting and removing specimens from high temperature vacuum furnaces

The apparatus comprises a high speed gate valve for isolating the interior of the furnance from an air lock chamber on the opposite side of the gate valve. The air lock chamber is provided with valve ports connected to a vacuum source, a source of inert quenching gas, and the atmosphere, respectively. Attached to the end of the air lock chamber away from the furnace is a cylindrical tube having disposed within it a rod carrying specimen pan at the end towards the furnace and having mounted at its top end an annular magnet having a diameter slightly less than the interior diameter of the tube. The top end of the tube is closed by a removeable cap. Encircling the tube in the vicinity of the magnet is a carbon steel ring which when axially moved along the tube causes the magnet to follow it and thereby controls the position of the rod and specimen pan within the tube.

Whitehead, C. W.↗
DOE OSTI2024

Fragment-based initialization for quantum subspace methods

Here, we present a novel quantum-classical algorithm called LAS-QKSD for multireference systems, by combining a classical localized active space (LAS) fragment-based multireference algorithm with the quantum Krylov subspace diagonalization (QKSD) method for quantum computers. The algorithm uses wave function information from a LAS self-consistent field (LASSCF) calculation to prepare an initial state with better overlap with the target ground state than the Hartree-Fock state. This is coupled with the use of QKSD to ultimately converge to the exact energy, providing faster convergence than starting from the Hartree-Fock state. Fragmentation has the two-fold benefit of fewer configurations on the classical side of the algorithm as well as fewer state preparation gates on the quantum side. First, we compare the LAS-QKSD method to the classical LASSCF method and to QKSD with a Hartree-Fock initial state. We then examine ways to load the LASSCF wave function using direct initialization and a QKSD-motivated spectral filtering approach. Finally, using a bimetallic complex, we show that the LAS-QKSD method is an efficient alternative to highly expensive complete active space SCF (CASSCF) calculations on strongly correlated systems.

D'Cunha, Ruhee↗
NASA NTRS2017

Spacecube V2.0 Micro Single Board Computer

A single board computer system radiation hardened for space flight includes a printed circuit board having a top side and bottom side; a reconfigurable field programmable gate array (FPGA) processor device disposed on the top side; a connector disposed on the top side; a plurality of peripheral components mounted on the bottom side; and wherein a size of the single board computer system is not greater than approximately 7 cm.times.7 cm.

Petrick, David J.↗
NASA NTRS1993

Effect of trapped ions in a gated time-of-flight apparatus

A three-mesh gate is used in a time-of-flight (TOF) apparatus to analyze the velocity of positive ions. Test results and a theoretical description are presented of an effect arising from trapping ions between meshes of a two-gate TOF velocity analyzer. The entrapped ions produce a side peak in the TOF spectra corresponding to faster ions. The onset and relative height of the side peak is dependent on the gating voltage and risetime of the pulsing electronics, while the relative intensity depends upon the velocity being sampled and the ratio of the gate width to duration.

Martus, K. E.↗
DOE OSTI2024

Heterogeneous Integration Technologies for High-temperature, High-density, Low-profile Power Modules of Wide Bandgap Devices in Electric Drive Applications (Final Technical Report)

The goal of this project is to develop packaging technologies for making high-temperature, high-density, and low-profile wide-bandgap (WBG) power electronics modules for electric drives. These modules are aimed at enabling the DOE’s University Consortium to reach its 2025 inverter targets of ≥ 100 kW/L and ≤ 2.7 $/kW. The specific objectives are to: design and fabricate SiC half-bridge power modules with double-sided cooling and parasitic inductances < 5 nH, heat flux density > 400 W/cm 2 , and working junction temperature of 200 o C; design, fabricate, and deliver a gate driver with double-sided cooled modules for the construction of a 100 kW/L inverter at Oak Ridge National Lab; and design and prototype intelligent gate drivers with integrated current sensor and a low-profile DC-DC power supply with air-core transformer for testing power modules at 200 o C junction temperature. We followed an iterative technical approach of design, simulation, fabrication, and testing of various versions of modules, current sensors, and power supply. The state-of-the-art silicon carbide devices rated at 1.2 kV and 149 A were packaged by sintered-silver bonding on an aluminum nitride direct-bond-copper substrate for high thermal conductivity, high working temperature, and high joint reliability. Porous silver posts were used to interconnect the device’s source pads to the other direct-bond-copper substrate for low mechanical stresses, ease of manufacturing, and double-sided cooling. A current sensor based on package parasitic inductance was developed to measure switching current. A dynamic feedback scheme was developed to compensate the effect of parasitic resistance and temperature variation. A constant-current class-E dc-dc converter with air-core transformer was developed. Air-core transformer was used due to the unavailability of magnetic core at high temperatures. Gate driver and power supply were integrated with the double-side cooled, high temperature SiC power modules for testing the modules at 200 o C junction temperature. Double-pulse and continuous testing of the integrated technologies validated the design and fabrication of the three component technologies. Throughout the project, we overcame the challenge for design verification caused by low prototyping yield, which then helped train the graduate students, the future workforce, to learn the engineering know-how for low-cost manufacturing of reliable products. Below is a summary of the major accomplishments of this project: development of a prototyping process for fabricating double-side cooled (1200 V, 149 A) SiC phase-leg modules capable of working to 200 o C Tj; simulation and experimental verification of the improvement of thermo-mechanical reliability of the double-side cooled SiC phase-leg module by using rigid encapsulant; design and experimental validation of a current sensor based on package parasitic inductance and a compensation solution for eliminating the effect of parasitic resistance; design and experimental validation of a low-profile power supply with six-output air-core transformer for gate driver; functional demonstration of a SiC phase-leg module integrated with its gate driver, current sensor, and an air-core power supply at 200 o C Tj in a double-pulse switching test setup and Buck converter continuous test setup; successful completion of six PhD and two MS students who are or will work at Apple Inc., Tesla Inc., Wolfspeed Inc., Microchip Inc., Monolithic Power Systems Inc., and LG Magna Inc.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2022

Conformational motions and ligand-binding underlying gating and regulation in IP 3 R channel

Inositol-1,4,5-trisphosphate receptors (IP3Rs) are activated by IP 3 and Ca 2+ and their gating is regulated by various intracellular messengers that finely tune the channel activity. Here, using single particle cryo-EM analysis we determined 3D structures of the nanodisc-reconstituted IP 3 R1 channel in two ligand-bound states. These structures provide unprecedented details governing binding of IP 3 , Ca 2+ and ATP, revealing conformational changes that couple ligand-binding to channel opening. Using a deep-learning approach and 3D variability analysis we extracted molecular motions of the key protein domains from cryo-EM density data. We find that IP 3 binding relies upon intrinsic flexibility of the ARM2 domain in the tetrameric channel. Our results highlight a key role of dynamic side chains in regulating gating behavior of IP 3 R channels. This work represents a stepping-stone to developing mechanistic understanding of conformational pathways underlying ligand-binding, activation and regulation of the channel.

59 BASIC BIOLOGICAL SCIENCES↗
NASA NTRS1975

Space-charge-limited solid-state triode

A solid-state triode is provided from a wafer of nearinstrinsic semiconductor material sliced into filaments of rectangular cross section. Before slicing, emitter and collector regions are formed on the narrow sides of the filaments, and after slicing gate regions are formed in arrow strips extending longitudinally along the midsections of the wide sides of the filaments. Contacts are then formed on the emitter, collector and gate regions of each filament individually for a single filament device, or in parallel for an array of filament devices to increase load current.

Shumka, A.↗
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗
DOE OSTI2026

Symmetry dilemmas in quantum computing for chemistry: A comprehensive analysis

Symmetry adaptation, universality, and gate efficiency are central but often competing requirements in quantum algorithms for electronic structure and many-body physics. For example, fully symmetry-adapted universal operator pools typically generate long and deep quantum circuits; gate-efficient universal operator pools generally break symmetries; and gate-efficient, fully symmetry-adapted operator pools may not be universal. In this work, we analyze such symmetry dilemmas both theoretically and numerically. On the theory side, we prove that the popular, gate-efficient operator pool consisting of singlet spin-adapted singles and perfect-pairing doubles is not universal when spatial symmetry is enforced. To demonstrate the strengths and weaknesses of the three types of pools, we perform numerical simulations using an adaptive algorithm paired with operator pools that are (i) fully symmetry-adapted and universal, (ii) fully symmetry-adapted and non-universal, and (iii) breaking a single symmetry and universal. Our numerical simulations encompass three physically relevant scenarios in which the target state is (i) the global ground state, (ii) the ground state crossed by a state differing in multiple symmetry properties, and (iii) the ground state crossed by a state differing in a single symmetry property. Our results show when symmetry-breaking but universal pools can be used safely, when enforcing at least one distinguishing symmetry suffices, and when a particular symmetry must be rigorously preserved to avoid variational collapse. Together, the formal and numerical analyses provide a practical guide for designing and benchmarking symmetry-adapted operator pools that balance universality, resource requirements, and robust state targeting in quantum simulations for chemistry.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS2008

Remote Raman Spectroscopy of Minerals at Elevated Temperature Relevant to Venus Exploration

We have used a remote time-resolved telescopic Raman system equipped with 532 nm pulsed laser excitation and a gated intensified CCD (ICCD) detector for measuring Raman spectra of a number of minerals at high temperature to 970 K. Remote Raman measurements were made with samples at 9-meter in side a high-temperature furnace by gating the ICCD detector with 2 micro-sec gate to minimize interference from blackbody emission from mineral surfaces at high temperature as well as interference from ambient light. A comparison of Raman spectra of gypsum (CaSO4.2H2O), dolomite (CaMg(CO3)2), and olivine (Mg2Fe2-xSiO4), as a function of temperature shows that the Raman lines remains sharp and well defined even in the high-temperature spectra. In the case of gypsum, Raman spectral fingerprints of CaSO4.H2O at 518 K were observed due to dehydration of gypsum. In the case of dolomite, partial mineral dissociation was observed at 973 K at ambient pressure indicating that some of the dolomite might survive on Venus surface that is at approximately 750 K and 92 atmospheric pressure. Time-resolved Raman spectra of low clino-enstatite (MgSiO3) measured at 75 mm from the sample in side the high-temperature furnace also show that the Raman lines remains sharp and well defined in the high temperature spectra. These high-temperature remote Raman spectra of minerals show that time-resolved Raman spectroscopy can be used as a potential tool for exploring Venus surface mineralogy at shorter (75 mm) and long (9 m) distances from the samples both during daytime and nighttime. The remote Raman system could also be used for measuring profiles of molecular species in the dense Venus atmosphere during descent as well as on the surface.

Sharma, Shiv K.↗