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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Investigation of Dynamic Temperature-Sensitive Electrical Parameters for Medium-Voltage Low-Current Silicon Carbide and Silicon Devices

This paper presents five dynamic temperature-sensitive electrical parameters (TSEPs) for the medium-voltage silicon carbide (SiC) and silicon (Si) devices. The theoretical temperature dependence of these parameters is analyzed. A test platform that enables to implement the temperature relevant dynamic characterization is developed. The tested TSEPs are summarized in terms of their relationship with junction temperature, drain/collector current, DC voltage, and external gate resistance. The comparison between the 3 kV 12 A Si IGBT and 3.3 kV 5 A SiC MOSFET with the identical TO-263 package is conducted. The results verify that the turn-off drain-source voltage switching rate achieves better thermal sensitivity for medium-voltage low-current SiC MOSFETs compared with Si IGBTs. Both the turn-on and turn-off delay time exhibit better thermal linearity for the two devices. The turn-off delay time further achieves five times better thermal sensitivity than the turn-on delay time for investigated medium-voltage SiC MOSFETs.

Ni, Ze↗
DOE OSTI2020

Accessing Atomic-scale Phosphorus Dopant Distribution in Precise Silicon Devices by Advanced STEM Imaging and Spectroscopy

The structural and chemical characterization at the atomic-scale plays a critical role in understanding the structure-property relationship in precise electrical devices such as those produced by atomic-precision advanced manufacturing (APAM). APAM, utilizing hydrogen lithography in a scanning tunneling microscope, offers a potential pathway to ultra-efficient transistors, and has been developed to produce phosphorus (P)-based donor devices integrated into bare Si substrates. Structural characterization of the buried, Si with P dopant (Si:P) delta-layer in the devices by scanning transmission electron microscopy (STEM), however, is a challenge due to similar atomic number and low concentration of the P dopants. In this paper, we describe several efforts of utilizing advanced STEM imagining and spectroscopic techniques to quantify the Si:P deltalayers. STEM imaging combining low-angle and high-angle annular dark-field (LAADF, HAADF) detectors as well as atomic-scale elemental mapping using energy-dispersive X-ray spectroscopy (EDS) are used to reveal the P and defect distribution across the delta-layer processed under various thermal conditions.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

Excess carrier concentration in silicon devices and wafers: How bulk properties are expected to accelerate light and elevated temperature degradation

Light and elevated temperature induced degradation (LeTID) is accelerated nearly linearly by the presence of excess carriers. It is therefore important to understand how excess carrier concentration (Δn) changes as a function of exposure conditions, materials properties, and sample structure. We simulate Δn as a function of wafer thickness and bulk minority carrier lifetime (τ) in solar cells and wafers using SCAPS and Quokka3. We also derive closed-form analytic expressions. For wafers, there is a near-linear relationship between Δn and τ or thickness, whereas for solar cells, Δn in the bulk may become limited by rear surface recombination. Thus, LeTID may progress more quickly in wafers than in cells, with a stronger dependence on τ. When comparing experiments, observed degradation rates must be corrected between samples or conditions to account for differences in Δn. This study demonstrates three tools to estimate the magnitude of such corrections, which can aid in the quantitative interpretation of LeTID data and performance predictions. Finally, while each tool yields similar results, there are advantages to each approach that must be weighed in terms of simplicity of inputs versus sophistication of treatment. Incomplete specification of back contact characteristics in commercial products is identified as an important contributor to uncertainty in expected LeTID rates.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Wide Bandgap Semiconductors for Extreme Temperature and Radiation Environments

With their greater voltage breakdowns, higher current limitations, and faster switching speeds, wide bandgap semiconductors are increasing in market application over the traditionally dominant silicon devices. Silicon carbide semiconductors have been increasing the efficiency and reducing the footprint of modern power electronics, and the increased electron mobility of gallium nitride semiconductors have been increasing the switching frequencies of radio frequency circuits. In extreme temperature (>225°C) applications and high radiation environments such as low earth orbit, deep space, and terrestrial nuclear reactors, silicon-based semiconductors degrade rapidly. Wide bandgap semiconductors are poised to disrupt the market for sensing, instrumentation, and communication circuitry in these hazardous environments by increasing the lifetime, safety, and reliability. This report outlines the advantages of using wide bandgap semiconductor materials in extreme temperature and radiation environments.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Fabrication-robust silicon photonic devices in standard sub-micron silicon-on-insulator processes

Perturbations to the effective refractive index from nanometer-scale fabrication variations in waveguide geometry plague high index-contrast photonic platforms; this includes the ubiquitous sub-micron silicon-on-insulator (SOI) process. Such variations are particularly troublesome for phase-sensitive devices, such as interferometers and resonators, which exhibit drastic changes in performance as a result of these fabrication-induced phase errors. In this Letter, we propose and experimentally demonstrate a design methodology for dramatically reducing device sensitivity to silicon width variations. We apply this methodology to a highly phase-sensitive device, the ring-assisted Mach–Zehnder interferometer (RAMZI), and show comparable performance and footprint to state-of-the-art devices, while substantially reducing stochastic phase errors from etch variations. This decrease in sensitivity is directly realized as energy savings by significantly reducing the required corrective thermal tuning power, providing a promising path toward ultra-energy-efficient large-scale silicon photonic circuits.

Rizzo, Anthony (ORCID:000000034752797X)↗
DOE OSTI2023

Investigation of the silicon coated film characteristics on tungsten surface in EAST fusion device

Siliconization using 10 % SiD 4 + 90 % He assisted by ion cyclotron range of frequency discharge (ICRF) or glow discharge (GD) was performed in EAST with full tungsten (W) diverters. It was found that the coated Si film on W sample at a higher baking temperature (160 °C) was smoother than that at a lower baking temperature (60 °C). This was mainly because physically adsorbed gaseous impurities were released at a higher baker temperature. This process improved the adhesion between the film and the surface of W. An increase in the ICRF working power from 20 kW to 40 kW further increased the Si content and the film thickness by 1.5 times. The cleaning efficiency of ICRF on the surface of the W sample before siliconization was higher at 40 kW than that at 20 kW, which facilitated the removal of oxides and other compounds from the surface of W. The ratio of silicon/oxygen (Si/O) and the thickness improved considerably due to greater ionization and deposition of SiD 4 . Additionally, siliconization via GD was more uniform and 1.5 nm thicker than that via ICRF, which was because of the greater working gas pressure, coating duration, and homogeneity in GD. These results might be used as a reference for evaluating the effect of siliconization on plasma performance and its application in fusion devices.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2025

Laser-Induced Spectral Diffusion of T Centers in Silicon Nanophotonic Devices

Color centers in silicon are emerging as spin-photon interfaces operating at telecommunication wavelengths. The nanophotonic device integration of silicon color centers via ion implantation leads to significant optical-linewidth broadening, which makes indistinguishable photon generation challenging. Here, we study the optical spectral diffusion of T centers in a silicon photonic crystal cavity. We investigate the linewidth-broadening timescales and origins by measuring the temporal correlations of the resonance frequency under different conditions. Spectral hole-burning measurements reveal no spectral broadening at short timescales from 102 ns to 725 ns. We probe broadening at longer timescales using a check pulse to herald the T-center frequency and a probe pulse to measure the frequency after a wait time. The optical resonance frequency is stable up to 3 ms in the dark. Laser pulses below the silicon band gap applied during the wait time lead to linewidth broadening. Our observations establish laser-induced processes as the dominant spectral-diffusion mechanism for T centers in devices and inform materials and feedback strategies for indistinguishable photon generation.

Zhang, Xueyue↗
DOE OSTI2022

Efficient black silicon photovoltaic devices with enhanced blue response

A photovoltaic (PV) device with improved blue response. The PV device includes a silicon substrate with an emitter layer on a light receiving side. The emitter layer has a low opant level such that it has sheet resistance of 90 to 170 ohm/sq. Anti-reflection in the PV device is provided solely by a nano-structured or black silicon surface on the light-receiving surface, through which the emitter is formed by diffusion. The nano structures of the black silicon are formed in a manner that does not result in gold or another high-recombination metal being left in the black silicon such as with metal-assisted etching using silver. The black silicon is further processed to widen these pores so as to provide larger nanostructures with lateral dimensions in the range of 65 to 150 nanometers so as to reduce surface area and also to etch away a highly doped portion of the emitter.

Oh, Jihun↗
DOE OSTI2025

Observation of interface piezoelectricity in superconducting devices on silicon

The development of superconducting quantum processors relies on understanding and mitigating decoherence in superconducting qubits. Piezoelectric coupling contributes to decoherence by mediating energy exchange between microwave photons and acoustic phonons. Although bulk centrosymmetric materials like silicon and sapphire are non-piezoelectric and commonly used as qubit substrates, the lack of centrosymmetry at interfaces may induce piezoelectric losses. This effect was predicted decades ago but never experimentally observed in superconducting devices. Here, we report interface piezoelectricity at aluminum-silicon junctions and demonstrate it as a significant loss channel in superconducting devices. Using aluminum interdigital transducers on silicon, we observe piezoelectric transduction from room to millikelvin temperatures, with an effective electromechanical coupling factor K 2 ≈ (3 ± 0.4) × 10−5%, comparable to weakly piezoelectric substrates. Modeling shows this mechanism limits qubit quality factors to Q ~ 10 4 − 10 8 , depending on surface participation and mode matching. These findings reveal interface piezoelectricity as a major dissipation channel and highlight the need for heterostructure and phononic engineering in next-generation superconducting qubits.

Zhou, Haoxin [University of California, Berkeley, ↗
DOE OSTI2021

Thin-film synthesis of superconductor-on-insulator A15 vanadium silicide

Abstract We present a new method for thin-film synthesis of the superconducting A15 phase of vanadium silicide with critical temperature higher than 13 K. Interdiffusion between a metallic vanadium film and the underlying silicon device layer in a silicon-on-insulator substrate, at temperatures between 650 and 750 °C, favors formation of the vanadium-rich A15 phase by limiting the supply of available silicon for the reaction. Energy dispersive X-ray spectroscopy, X-ray photoelectron spectroscopy, and X-ray diffraction verify the stoichiometry and structure of the synthesized thin films. We measure superconducting critical currents of more than 10 6 amperes per square centimeter at low temperature in micron-scale bars fabricated from the material, and an upper critical magnetic field of 20 T, from which we deduce a superconducting coherence length of 4 nm, consistent with previously reported bulk values. The relatively high critical temperature of A15 vanadium silicide is an appealing property for use in silicon-compatible quantum devices and circuits.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Readout optimization of multi-amplifier sensing charge-coupled devices for single-quantum measurement

The non-destructive readout capability of the Skipper Charge Coupled Device (CCD) has been demonstrated to reduce the noise limitation of conventional silicon devices to levels that allow single-photon or single-electron counting. The noise reduction is achieved by taking multiple measurements of the charge in each pixel. These multiple measurements come at the cost of extra readout time, which has been a limitation for the broader adoption of this technology in particle physics, quantum imaging, and astronomy applications. This work presents recent results of a novel sensor architecture that uses multiple non-destructive floating-gate amplifiers in series to achieve sub-electron readout noise in a thick, fully-depleted silicon detector to overcome the readout time overhead of the Skipper-CCD. This sensor is called the Multiple-Amplifier Sensing Charge-Coupled Device (MAS-CCD) can perform multiple independent charge measurements with each amplifier, and the measurements from multiple amplifiers can be combined to further reduce the readout noise. We will show results obtained for sensors with 8 and 16 amplifiers per readout stage in new readout operations modes to optimize its readout speed. The noise reduction capability of the new techniques will be demonstrated in terms of its ability to reduce the noise by combining the information from the different amplifiers, and to resolve signals in the order of a single photon per pixel. The first readout operation explored here avoids the extra readout time needed in the MAS-CCD to read a line of the sensor associated with the extra extent of the serial register. The second technique explore the capability of the MAS-CCD device to perform a region of interest readout increasing the number of multiple samples per amplifier in a targeted region of the active area of the device.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2022

Side-lobe reduction by cascading Bragg grating filters on a Si-photonic chip

Bragg-grating based cavities and coupler designs present opportunities for flexible allocation of bandwidth and spectrum in silicon photonic devices. Integrated silicon photonic devices are moving toward mainstream, mass adoption, leading to the need for compact Bragg grating based designs. In this work we present a design and experimental validation of a cascaded contra-directional Bragg-grating coupler with a measured main lobe to side-lobe contrast of 12.93 dB. This level of performance is achieved in a more compact size as compared to conventional apodized gratings, and a similar design philosophy can be used to improve side-lobe reduction in grating-based mirror design for on-chip lasers and other cavity-based designs as well.

42 ENGINEERING↗
DOE OSTI2025

Variable Bragg x-ray beam splitters

Beam splitters are utilized in a variety of advanced x-ray instruments and are essential for extending quantum optics techniques to x rays. A new fabrication method has produced thinned Bragg diffracting silicon devices with variable reflectivity and transmission coefficients and negligible absorption losses. Diffraction measurements confirm that silicon continues to exhibit perfect crystal diffraction even for thicknesses below two microns. Devices are machined from standard wafers, with the thinned regions contained within the robust frame of an unperturbed crystal for ease of handling.

Powers, L. T. (ORCID:000900047481248X)↗
DOE OSTI2024

Future of plasma etching for microelectronics: Challenges and opportunities

Plasma etching is an essential semiconductor manufacturing technology required to enable the current microelectronics industry. Along with lithographic patterning, thin-film formation methods, and others, plasma etching has dynamically evolved to meet the exponentially growing demands of the microelectronics industry that enables modern society. At this time, plasma etching faces a period of unprecedented changes owing to numerous factors, including aggressive transition to three-dimensional (3D) device architectures, process precision approaching atomic-scale critical dimensions, introduction of new materials, fundamental silicon device limits, and parallel evolution of post-CMOS approaches. The vast growth of the microelectronics industry has emphasized its role in addressing major societal challenges, including questions on the sustainability of the associated energy use, semiconductor manufacturing related emissions of greenhouse gases, and others. The goal of this article is to help both define the challenges for plasma etching and point out effective plasma etching technology options that may play essential roles in defining microelectronics manufacturing in the future. The challenges are accompanied by significant new opportunities, including integrating experiments with various computational approaches such as machine learning/artificial intelligence and progress in computational approaches, including the realization of digital twins of physical etch chambers through hybrid/coupled models. These prospects can enable innovative solutions to problems that were not available during the past 50 years of plasma etch development in the microelectronics industry. To elaborate on these perspectives, the present article brings together the views of various experts on the different topics that will shape plasma etching for microelectronics manufacturing of the future.

Engineering↗
DOE OSTI2022

Low voltage AC electroluminescence in silicon MOS capacitors

Low power silicon based light source and detector are attractive for on-chip photonic circuits given their ease of process integration. However, conventional silicon light emitting diodes emit photons with energies near the band edge where the corresponding silicon photodetectors lack responsivity. On the other hand, previously reported hot carrier electroluminescent silicon devices utilizing a reverse biased diode require high operating voltages. Here, we investigate hot carrier electroluminescence in silicon metal–oxide–semiconductor capacitors operating under transient voltage conditions. Further, during each voltage transient, large energy band bending is created at the edge of the source contact, much larger than what is achievable at a steady state. As a result, electrons and holes are injected efficiently from a single source contact into the silicon channel at the corresponding voltage transient, where they subsequently undergo impact ionization and phonon-assisted interband recombination. Notably, we show low voltage operation down to 2.8 V by using a 20 nm thick high-κ gate dielectric. We show further voltage scaling is possible by reducing the gate dielectric thickness, thus presenting a low voltage platform for silicon optoelectronic integrated circuits.

42 ENGINEERING↗
DOE OSTI2026

Performance Modeling of Tandem Photovoltaics: A Yearlong Outdoor Degradation Analysis of a Ga⁢As//Si Minimodule

We present a performance modeling and degradation analysis framework for tandem photovoltaic modules, building upon established procedures for crystalline silicon devices and adapting them to account for the spectral sensitivity of multijunction technologies. The methodology employs filter criteria to select outdoor measurements close to standard test conditions (STC) under stable spectral and ambient conditions, followed by normalization of power production data with corrections for temperature, irradiance, and precipitable water vapor. We demonstrate this framework using a mechanically stacked four-terminal gallium arsenide (Ga⁢As) // silicon (Si) tandem solar minimodule deployed outdoors from October 2019 to January 2021 in Golden, Colorado, USA. We determined degradation rates of −4.1 ±0.2%/year for the Ga⁢As subcell and −2.5 ±0.9%/year for the Si subcell, with analysis of individual performance metrics indicating that packaging degradation, particularly delamination, was the dominant failure mode. Simulations using PVcircuit, an open-source equivalent-circuit solver, confirmed these findings. The presented methodology provides a reproducible foundation for performance modeling and degradation analysis of emerging tandem technologies.

14 SOLAR ENERGY↗