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This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.
A reproducible process is described for growing a thick single-crystal layer of cubic SiC on a single-crystal Si wafer by chemical vapor deposition. A buffer layer, grown in situ, is used between the cubic SiC and the Si substrate to minimize the effect of lattice mismatch. Layers of up to 34 microns thick and several sq cm in area have been grown. Wafers are obtained by chemically removing the Si substrates from the grown layers. Excellent electron channeling patterns produced by these wafers indicate very good crystal quality. Preliminary electrical measurements have yielded electron mobilities up to 380 sq cm/Vs.
The solar power satellite (SPS) concept, under evaluation by NASA since 1974, is discussed. A typical system providing a total of 10,000 MW of electrical power to the ground receiving stations is considered. Energy conversion systems, including the photovoltaic device category using single-crystal silicon cells, are taken into account, as are the 2.45-GHz microwave power-transmission link and the ground receiver (or rectenna). Concepts involving space construction of the satellite's large structures (5 x 25 km) are described, noting that a process similar to the familiar roll-forming of light sheet metal parts has been adapted to the space environment. Transportation vehicles are discussed, including the Space Shuttle planned to reach 60 flights per year by the mid 1980's. Electrical power forecasts and advanced systems cost projections are analyzed, together with a description of costs estimates. The indirect economics of energy research and development, and the present NASA/DOE SPS program are noted.
After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the areas of crystal growth and device fabrication technology. High quality single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.
After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the area of crystal growth and device fabrication technology. High quality of single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.
High-efficiency, thin-film InP solar cells grown heteroepitaxially on GaAs and Si single-crystal bulk substrates are being developed as a means of eliminating the problems associated with using single-crystal InP substrates. A novel device structure employing a compositionally graded Ga(x)In(1-x)As layer between the bulk substrate and the InP cell layers is used to reduce the dislocation density and improve the minority carrier properties in the InP. The structures are grown in a continuous sequence of steps using computer-controlled atmospheric pressure metalorganic vapor phase epitaxy (APMOVPE). Dislocation densities as low as 3 x 10(exp 7) sq cm and minority carrier lifetimes as high as 3.3 ns are achieved in the InP layers with this method using both GaAs or Si substrates. Structures prepared in this fashion are also completely free of microcracks. These results represent a substantial improvement in InP layer quality when compared to heteroepitaxial InP prepared using conventional techniques such as thermally cycled growth and post-growth annealing. The present work is is concerned with the fabrication and characterization of high-efficiency, thin-film InP solar cells. Both one-sun and concentrator cells were prepared for device structures grown on GaAs substrates. One-cell cells have efficiencies as high as 13.7 percent at 25 C. However, results for the concentrator cells are emphasized. The concentrator cell performance is characterized as a function of the air mass zero (AM0) solar concentration ratio and operating temperature. From these data, the temperature coefficients of the cell performance parameters are derived as a function of the concentration ratio. Under concentration, the cells exhibit a dramatic increase in efficiency and an improved temperature coefficient of efficiency. At 25 C, a peak conversion efficiency of 18.9 percent is reported. At 80 C, the peak AM0 efficiency is 15.7 percent at 75.6 suns. These are the highest efficiencies yet reported for InP heteroepitaxial cells. Approaches for further improving the cell performance are discussed.
Infrared radiation at wavelengths of 1-2 microns has been detected in a new device labeled the layered internal photoemission sensor. The device structure, which is grown by molecular beam epitaxy, incorporates epitaxial CoSi2 particles with dimensions of 10-50 nm. Radiation absorbed by these particles photoexcites carriers into a surrounding single-crystal silicon matrix. A peak quantum efficiency of 1.3 percent is measured, which is approximately six times higher than in planar CoSi2 Schottky diodes with 5-nm silicide thickness.
Thin buffer layer of SiC minimizes effects of lattice mismatch. Approach consists of growing single-crystal layer of cubic SiC on single-crystal silicon (Si) wafer by chemical-vapor deposition (CVD). Process developed for production of large-area single-crystal wafers of cubic silicon carbide (SiC) for semiconductor devices; also used to make devices themselves. Applications include electronics for high temperature (up to 900 C) and electronics for very high frequencies.
A new approach to seeing in the dark is described which is based on the principles of nonlinear optics employing a crystal such as lithium iodate. A nonlinear optical device capable of producing photons at higher frequencies from lower-frequency incident light is shown to upconvert infrared light directly into visible light. The major advantages of the infrared upconversion process is that it permits the infrared signal to be detected by photon-counting devices presently available for the visible spectral region, and that it can provide sensitivity to infrared radiation without the need for cryogenic cooling of the detector used. Early works on infrared upconversion are reviewed. The development of applications is discussed as to astronomical spectroscopy and infrared image upconversion involving either angular or positional resolution elements. The demonstration of infrared upconversion in rectangular waveguides of single-crystal GaAs by Anderson et al. (1971) indicates future possibilities in upconversion by the use of integrated optics devices.
Refined techniques for surface texturizing, back surface field and back surface reflector formation were evaluated for use with shallow junction, single-crystal silicon solar cells. Each process was characterized individually and collectively as a function of device thickness and bulk resistivity. Among the variables measured and reported are open circuit voltage, short circuit current and spectral response. Substantial improvements were obtained by the utilization of a low cost aluminum paste process to simultaneously remove the unwanted n(+) diffused region, form the back surface field and produce an ohmic contact metallization. The highly effective BSF which results from applying this process has allowed fabrication of cells 0.05 mm thick with initial outputs as high as 79.5 mW/4 sq cm (28 C, AM0) and superior electron radiation tolerance. Cells of 0.02 mm to 0.04 mm thickness have been fabricated with power to mass ratios well in excess of 2 watts per gram.
In connection with the relatively poor insulating characteristics of the native oxides of most III-V compound semiconductors, there has been interest in the development of deposited dielectric layers for surface passivation and MOS device fabrication on III-V compound semiconductor substrates. The chemical system of SiO2 deposited on single-crystal InSb substrates has been proposed for the fabrication of IR CCD. The considered investigation is concerned with a detailed examination of the chemical nature of the interactions between deposited and native oxides using X-ray photoelectron spectroscopy (XPS) in conjunction with a chemical-etching technique for depth profiling. The compositional structure of the interfaces obtained in the SiO2/native oxide/InSb system is derived on the basis of an intensity analysis of XPS spectra. Thermal oxidation of the InSb substrate is found to result in an In-rich native oxide and excess elemental Sb at the native oxide/substrate interface.
Efficient solar cells of indium tin oxide (ITO)/InP have been fabricated using dc magnetron deposition of the ITO into single-crystal InP substrates. Efficiencies of over 16.5 percent have been achieved, the highest ever recorded for devices of this construction. The results of studies of the annealing behavior of the cells and observations of interfacial changes using Raman spectroscopy and secondary ion mass spectroscopy, together with measurements of light and dark current/voltage and quantum efficiency characteristics, are used to model the behavior of the cells and explain their lack of sensitivity to fabrication conditions.
Crystalline layers grown in commercial apparatus. Experiments show CrSi2 grown on (111) face of single-crystal Si substrate by molecular-beam epitaxy. Epitaxial CrSi2 produced thus far not in desired single-crystal form. Because CrSi2 semiconductor with band gap of 0.3 eV, experimental process potential for monolitic integration of microelectronic devices based on CrSi2 (e.g., infrared detectors) with signal-processing circuitry based on Si.
Improved SiC chemical vapor deposition films of both 3C and 6H polytypes were grown on vicinal (0001) 6H-SiC wafers cut from single-crystal boules. These films were produced from silane and propane in hydrogen at one atmosphere at a temperature of 1725 K. Among the more important factors which affected the structure and morphology of the grown films were the tilt angle of the substrate, the polarity of the growth surface, and the pregrowth surface treatment of the substrate. With proper pregrowth surface treatment, 6H films were grown on 6H substrates with tilt angles as small as 0.1 degrees. In addition, 3C could be induced to grow within selected regions on a 6H substrate. The polarity of the substrate was a large factor in the incorporation of dopants during epitaxial growth. A new growth model is discussed which explains the control of SiC polytype in epitaxial growth on vicinal (0001) SiC substrates.
New fabrication method produces pinhole-free film of cobalt silicide on silicon substrate. In new method, cobalt and silicon evaporated from electron-beam sources onto substrate of silicon having <111> crystal orientation. Materials deposited in stoichiometric ratio of two silicon atoms to one of cobalt, yielding single-crystal CoSi2 film 5 to 10 nm thick. Layer of amorphous silicon 1 to 2 nm thick deposited on CoSi2. Specimen then annealed at 550 degree C for 10 min. Absence of pinholes critical to operation of multilayer devices employing CoSi2 layers, such as metal base transistor.
Report describes experiments on crack growth in single-crystal silicon at room temperature in air. Crack growth in (111) cleavage plane of wafers, 50 by 100 by 0.76 mm in dimension, cut from Czochralski singlecrystal silicon studied by double-torsion load-relaxation method and by acoustic-emission measurements. Scanning electron microscopy and X-ray topography also employed. Results aid in design and fabrication of silicon photovoltaic and microelectronic devices.
Large-area photovoltaic solar cells based on direct current magnetron sputter deposition of indium tin oxide (ITO) into single-crystal p-InP substrates demonstrated both the radiation hardness and high performance necessary for extraterrestrial applications. A small-scale production project was initiated in which approximately 50 ITO/InP cells are being produced. The procedures used in this small-scale production of 4-sq cm ITO/InP cells are presented and discussed. The discussion includes analyses of performance range of all available production cells, and device performance data of the best cells thus far produced. Additionally, processing experience gained from the production of these cells is discussed, indicating other issues that may be encountered when large-scale productions are begun.
To achieve higher Si solar cell efficiencies (greater than 20%), better single-crystal Si must be produced. It is believed possible to bring Cz (Czochralski) Si up to the same low recombination level as FZ (Float Zone) Si. It is also desirable that solar cell Si meet the following requirements: long minority carrier lifetime (0.2 ohm-cm p-type with tau less than 500 microsec); repeatedly uniform lifetime (not spread from 50 to 1000 microsec); a lifetime that does not decrease during normal device processing; a silicon wafer sheet that is flat and stays throughout normal device processing; uniform and reasonable mechanical strength; and, manufacture at low cost (less than $50/sq m).