Detecting Subtle Soft Shorts in Li-ion Cells
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soft short circuits↗
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Design Considerations for Practical Li-S Batteries for Electric Aviation
The development of high-energy, high-safety, and high-power batteries beyond electric automotive standards is critical for future electric aviation applications. Non-volatile solid-state electrolytes (SSE) offer many promising advantages over traditional flammable liquid electrolytes. Solid-state electrolytes may be an enabling technology for certain battery chemistries by preventing detrimental interactions with liquid electrolytes, for example prevention of the dissolution of intermediates in lithium-sulfur common in traditional liquid organic solvents. However, significant manufacturing challenges must be overcome before the adoption of such technology. This research was conducted to identify processing techniques for producing solid-state battery components with practical dimensions and weights for enabling high specific energy cells. Traditional research has identified a range of very high theoretical ionic conductivities but are impractical due to their instability or inability to be manufactured. Electrolytes explored in this study were produced as sulfide-polymer composites with densified thicknesses below 40 micron using a tape-casting technique and thermoplastic elastomer binder. The combination of high chemical compatibility and flexibility produced robust films that had moderate impact on the ionic conductivity but was capable of dramatically reducing the parasitic mass. Despite minimal conductivity losses, films were produced 10-15 times thinner than comparable bulk powder electrolytes thus leading to overall lower film resistance. Conductivity is maintained above 0.2mS/cm for composite electrolytes. Through the analysis of materials based on their physical properties, such as density, practical cells can be designed. Based on this, low density sulfide-solid-state electrolytes are a promising candidate for achieving the energy and safety metrics for electric aviation, however, further optimization of cathode microstructure and composite processing will be required to achieve the high power metrics and will be the focus of further studies. Additionally, fabrication challenges arise when utilizing metallic lithium foil, due to its soft nature, as overflow and mechanical short circuit can occur on assembly which remains a challenge to overcome before metallic lithium anodes can be fully realized.
batteries↗
Are Soft Short Tests Good Indicators of Internal Li-ion Cell Defects?
The self discharge test at full state of charge, may not be a good one to detect subtle defects since the li-ion chemistry has the highest self discharge at full state of charge. One should characterize self discharge versus storage time for each cell manufacturer/design to differentiate between normal self discharge and that due to a subtle manufacturing defect. The various soft short test methods indicate that if this test is carried out at full discharge (0% SOC) with all capacity removed (by lowering the current load in a stepwise manner to the same end of discharge voltage), then the cells need to be placed in storage for more than 72 hours to get a good analysis on the presence of subtle defects since it takes more than 72 hours to achieve voltage stabilization. If the cells are to be charged up even to a small percentage (ex. 1%), 72 hours are sufficient to determine issues. However, the pass/fail criteria should be based on a valid OCV decline. Less than 10 mV voltage decline is not a good method to detect subtle defects. As mentioned in the first bullet, self discharge is a competing reaction when a charge is introduced and hence a characterization of the self discharge versus storage time is required to fully correlate voltage decline to a failure due to a subtle defect. Soft short test method cannot be relied on for defect detection because cells with and without voltage decline seemed to have similar defects and characteristics. Screening methods such as internal resistance and capacity as well as a 3-sigma range for OCV, mass and dimensions should be used to screen out outliers. A very critical aspect in the understanding of subtle defects is to carry out destructive analysis of cells from every lot to confirm the quality of production and screen all cells and batteries in a stringent manner to have a high quality set of flight cells. Self Discharge Test: Fully charged cells shall be placed in Open circuit stand for 72 hours (OCV measurement twice a day); continue for total of 14 days with 1 reading per day 2. Soft Short Test 1: Fully charge; cells discharged to manufacturer's end of disch. Voltage (EODV) cutoff at C/5 rate; stand for 30 minutes; discharge with C/500 to the same EODV. stand for another 30 minutes; discharge the cells again using C/1000 current to the same EODV. OCV measurements twice a day for 72 hours and then for total of 14 days (data collection same as in 1.) 3. Soft Short Test 2: Fully charge; cells discharged to the manuf. EODV with a C/13 constant current; provide a 10 hour rest, discharge again to the same EODV with a current of C/250, provide a 10 hour rest, discharge again using a C/250 rate, provide a 24 hour rest, charge using C/250 to 3.15 V (for ~12 hours). OCV measurements twice a day for at 72 hours. (data collection same as in 1.) 4. Soft Short Test 3: Fully charge; cells shall be discharged using C/10 current to manuf. EODV. Allow the cell to remain at Open circuit for 10 seconds. Discharge the cell at C/20 rate to the same EODV, hold open circuit for 24 hours. Discharge the cells at C/200 rate to the same end of voltage cutoff and hold open circuit for 24 hours. Discharge the cells one more time at C/200 rate to the same EODV and hold open circuit for 36 hours. Charge at C/200 rate to 3.15 V and hold for 3 days. Record OCV during the open circuit stand periods every 12 hours and at the beginning and end of the 3 day hold (include the 12 hour OCV recording during this time also). Capacity Cycling: Cells with declining voltages - one cell from each manufacturer chosen for cycling Destructive Physical Analysis (DPA): Cells with and without decline chosen from each lot for DPA.
Jeevarajan, J.↗
Voltage controller/current limiter for ac
Circuit protects ac power systems for overload failures, limits power surge and short-circuit currents to 150 percent of steady state level, regulates ac output voltage, and soft starts loads. Limiter generates dc error signal in response to line fluctuations and dumps power when overload is reached. Device is inserted between ac source and load.
Wu, T. T.↗
Study of a High Voltage Ion Engine Power Supply
A complete laboratory breadboard version of a ion engine power converter was built and tested. This prototype operated on a line voltage of 80-120 Vdc, and provided output ratings of 1100 V at 1.8 kW, and 250 V at 20 mA. The high-voltage (HV) output voltage rating was revised from the original value of 1350 V at the beginning of the project. The LV output was designed to hold up during a 1-A surge current lasting up to 1 second. The prototype power converter included a internal housekeeping power supply which also operated from the line input. The power consumed in housekeeping was included in the overall energy budget presented for the ion engine converter. HV and LV output voltage setpoints were commanded through potentiometers. The HV converter itself reached its highest power efficiency of slightly over 93% at low line and maximum output. This would dip below 90% at high line. The no-load (rated output voltages, zero load current) power consumption of the entire system was less than 13 W. A careful loss breakdown shows that converter losses are predominately Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) conduction losses and HV rectifier snubbing losses, with the rectifier snubbing losses becoming predominant at high line. This suggests that further improvements in power efficiency could best be obtained by either developing a rectifier that was adequately protected against voltage overshoot with less snubbing, or by developing a pre-regulator to reduced the range of line voltage on the converter. The transient testing showed the converter to be fully protected against load faults, including a direct short-circuit from the HV output to the LV output terminals. Two currents sensors were used: one to directly detect any core ratcheting on the output transformer and re-initiate a soft start, and the other to directly detect a load fault and quickly shut down the converter for load protection. The finished converter has been extensively fault tested without failure. The finished converter has been packaged suitable for use as a laboratory prototype for further testing. The finished converter is readily transportable. An article on design issues for high voltage converters for ion engines is included as an attachement.
Stuart, Thomas A.↗
Performance and Abuse Testing of 5 Year Old Low Rate and Medium Rate Lithium Thionyl Chloride Cells
Most cells survived the 3 amp (A) over-discharge at room temperature for 2 hours. The cell that failed was the LTC-114 after high rate discharge of 500 mA similar to the results of the 1 A over-discharge test. Most cells opened during 0.05 Ohm short circuit test without incident but three LTC-111 cells exploded apparently due to a lack of a thermal cutoff switch. The LTC-114 cells exposed to a hard short of 0.05 Ohms recovered but the LTC-114 cells exposed to a soft short of 1 Ohm did not. This is probably due to the activation of a resetable fuse during a hard short. Fresh cells tend to survive exposure to higher temperatures than cells previously discharged at high rate (1 Amp). LTC-111 cells tend to vent at lower temperatures than the all LTC-114 cells and the LTC-115 cells that were previously discharged at rates exceeding 1 Amp.
Frerker, Rick↗
Trellises and Trellis-Based Decoding Algorithms for Linear Block Codes
A code trellis is a graphical representation of a code, block or convolutional, in which every path represents a codeword (or a code sequence for a convolutional code). This representation makes it possible to implement Maximum Likelihood Decoding (MLD) of a code with reduced decoding complexity. The most well known trellis-based MLD algorithm is the Viterbi algorithm. The trellis representation was first introduced and used for convolutional codes [23]. This representation, together with the Viterbi decoding algorithm, has resulted in a wide range of applications of convolutional codes for error control in digital communications over the last two decades. There are two major reasons for this inactive period of research in this area. First, most coding theorists at that time believed that block codes did not have simple trellis structure like convolutional codes and maximum likelihood decoding of linear block codes using the Viterbi algorithm was practically impossible, except for very short block codes. Second, since almost all of the linear block codes are constructed algebraically or based on finite geometries, it was the belief of many coding theorists that algebraic decoding was the only way to decode these codes. These two reasons seriously hindered the development of efficient soft-decision decoding methods for linear block codes and their applications to error control in digital communications. This led to a general belief that block codes are inferior to convolutional codes and hence, that they were not useful. Chapter 2 gives a brief review of linear block codes. The goal is to provide the essential background material for the development of trellis structure and trellis-based decoding algorithms for linear block codes in the later chapters. Chapters 3 through 6 present the fundamental concepts, finite-state machine model, state space formulation, basic structural properties, state labeling, construction procedures, complexity, minimality, and sectionalization of trellises. Chapter 7 discusses trellis decomposition and subtrellises for low-weight codewords. Chapter 8 first presents well known methods for constructing long powerful codes from short component codes or component codes of smaller dimensions, and then provides methods for constructing their trellises which include Shannon and Cartesian product techniques. Chapter 9 deals with convolutional codes, puncturing, zero-tail termination and tail-biting.Chapters 10 through 13 present various trellis-based decoding algorithms, old and new. Chapter 10 first discusses the application of the well known Viterbi decoding algorithm to linear block codes, optimum sectionalization of a code trellis to minimize computation complexity, and design issues for IC (integrated circuit) implementation of a Viterbi decoder. Then it presents a new decoding algorithm for convolutional codes, named Differential Trellis Decoding (DTD) algorithm. Chapter 12 presents a suboptimum reliability-based iterative decoding algorithm with a low-weight trellis search for the most likely codeword. This decoding algorithm provides a good trade-off between error performance and decoding complexity. All the decoding algorithms presented in Chapters 10 through 12 are devised to minimize word error probability. Chapter 13 presents decoding algorithms that minimize bit error probability and provide the corresponding soft (reliability) information at the output of the decoder. Decoding algorithms presented are the MAP (maximum a posteriori probability) decoding algorithm and the Soft-Output Viterbi Algorithm (SOVA) algorithm. Finally, the minimization of bit error probability in trellis-based MLD is discussed.
Lin, Shu↗
Vertical bloch line memory
Vertical Bloch Line (VBL) memory is a recently conceived, integrated, solid-state, block-access, VLSI memory which offers the potential of 1Gbit/sq cm real storage density, gigabit per second data rates, and sub-millisecond average access times simultaneously at relatively low mass, volume, and power values when compared to alternative technologies. VBL's are micromagnetic structures within magnetic domain walls which can be manipulated using magnetic fields from integrated conductors. The presence or absence of VBL pairs are used to store binary information. At present, efforts are being directed at developing a single-chip memory using 25Mbit/sq cm technology in magnetic garnet material which integrates, at a single operating point, the writing, storage, reading, and amplification functions needed in a memory. This paper describes the current design architecture, functional elements, and supercomputer simulation results which are used to assist the design process. The current design architecture uses three metal layers, two ion implantation steps for modulating the thickness of the magnetic layer, one ion implantation step for assisting propagation in the major line track, one NiFe soft magnetic layer, one CoPt hard magnetic layer, and one reflective Cr layer for facilitating magneto-optic observation of magnetic structure. Data are stored in a series of elongated magnetic domains, called stripes, which serve as storage sites for arrays of VBL pairs. The ends of these stripes are placed near conductors which serve as VBL read/write gates. A major line track is present to provide a source and propagation path for magnetic bubbles. Writing and reading, respectively, are achieved by converting magnetic bubbles to VBL's and vice versa. The output function is effected by stretching a magnetic bubble and detecting it magnetoresistively. Experimental results from the past design cycle created four design goals for the current design cycle. First, the bias field ranges for the stripes and the major line needed to be matched. Second, the magnetic field barrier between the stripe and the read/write gates needed to be reduced. Third, current conductor routing needed to be improved to reduce occurrences of open-circuiting, short-circuiting, and eddy-current shielding. Fourth, a modified Co-alloy was needed with an increased coercivity and controlled magnetization to allow VBL stabilization to occur without affecting stripe stability.
Katti, R.↗
RH1020 Single Event Clock Upset Summary Report
This report summarizes the testing and analysis of "single event clock upset' in the RH1020. Also included are SEU-rate predictions and design recommendations for risk analysis and reduction. The subject of "upsets" in the RH1020 is best understood by using a model consisting of a global clock buffer and a D-type flip-flop as the basic memory unit. The RH1020 is built on the ACT 1 family architecture. As such, it has one low-skew global clock buffer with a TTL-level input threshold that is accessed via a single dedicated pin. The clock signal is driven to full CMOS levels, buffered, and sent to individual row buffers with one buffer per channel. For low-skew performance, the outputs of all of the RH1020 row buffers are shorted together via metal lines, as is done in the A1020B. All storage in the RH1020 consists of routed flip-flops, constructed with multiplexors and feedback through the routing segments. A simple latch can be constructed from a single (combinatorial or C) module; an edge-triggered flip-flop is constructed using two concatenated latches. There is no storage in the I/O modules. The front end of the clock buffering circuitry, at a common point relative to the row buffer, is a sub-circuit that was determined to be the most susceptible to heavy ions. This is due, in part, to its smaller transistors compared to the rest of the circuitry. This conclusion is also supported by SPICE simulations and an analysis of the heavy ion data, described in this report. The edge triggered D flip-flop has two single-event-upset modes. Mode one, called C-module upset, is caused by a heavy ion striking the C-module's sensitive area on the silicon and produces a soft single bit error at the output of the flip-flop. Mode two, called clock upset, is caused by a heavy ion strike on the clock buffer, generating a runt pulse interpreted as a false clock signal and consequently producing errors at the flip-flop outputs. C-module upset sensitivity in the RH1020 is essentially the same as that of its ACT 1 siblings (A1020, A1020A and A1020B), which were well tested, analyzed, and documented in the literature.
Katz, Richard B.↗