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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options

Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.

42 ENGINEERING↗
DOE OSTI2015

Development FD-SOI MOSFET Amplifiers for Integrated Read-Out Circuit of Superconducting-Tunnel-Junction Single-Photon-Detectors

We proposed a new high-resolution single-photon infrared spectrometer for search for radiative decay of cosmic neutrino background (CνB). The superconducting-tunnel-junctions(STJs) are used as a single-photon counting device. Each STJ consists of Nb/Al/Al x O y /Al/Nb layers, and their thicknesses are optimized for the operation temperature at 370 mK cooled by a 3 He sorption refrigerator. Our STJs achieved the leak current 250 pA, and the measured data implies that a smaller area STJ fulfills our requirement. FD-SOI MOSFETs are employed to amplify the STJ signal current in order to increase signal-to-noise ratio (S/N). FD-SOI MOSFETs can be operated at cryogenic temperature of 370 mK, which reduces the noise of the signal amplification system. FD-SOI MOSFET characteristics are measured at cryogenic temperature. The Id-Vgs curve shows a sharper turn on with a higher threshold voltage and the Id-Vds curve shows a nonlinear shape in linear region at cryogenic temperature. Taking into account these effects, FD-SOI MOSFETs are available for read-out circuit of STJ detectors. The bias voltage for STJ detectors is 0.4 mV, and it must be well stabilized to deliver high performance. We proposed an FD-SOI MOSFET-based charge integrated amplifier design as a read-out circuit of STJ detectors. The requirements for an operational amplifier used in the amplifier is estimated using SPICE simulation. The op-amp is required to have a fast response (GBW ≥ 100 MHz), and it must have low power dissipation as compared to the cooling power of refrigerator.

47 OTHER INSTRUMENTATION↗
DOE OSTI2016

Test results of a counting type SOI device for a new x-ray area detector

Development of a new detector using Silicon-On-Insulator (SOI) technology has been started in the Photon Factory, KEK. The aim of this project is to develop a pulse-counting-type X-ray detector that can be used in synchrotron radiation experiments using soft X-rays. We started to make a Test Element Group of SOI chip, which is called CPIXPTEG1 and evaluated its performance. We succeeded in readout of output signals for 16 keV X-rays from the SOI chips. We also found that the middle-SOI structure was effective against a signal distortion caused by hole traps in the buried oxide layer.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2015

Density dependence of electron mobility in the accumulation mode for fully depleted SOI films

The electron mobility µ{sub eff} in the accumulation mode is investigated for undepleted and fully depleted double-gate n{sup +}–n–n{sup +} silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFET). To determine the range of possible values of the mobility and the dominant scattering mechanisms in thin-film structures, it is proposed that the field dependence of the mobility µ{sub eff} be replaced with the dependence on the density N{sub e} of induced charge carriers. It is shown that the dependences µ{sub eff}(N{sub e}) can be approximated by the power functions µ{sub eff}(N{sub e}) ∝ N{sub e}{sup -n}, where the exponent n is determined by the chargecarrier scattering mechanism as in the mobility field dependence. The values of the exponent n in the dependences µ{sub eff}(N{sub e}) are determined when the SOI-film mode near one of its surfaces varies from inversion to accumulation. The obtained results are explained from the viewpoint of the electron-density redistribution over the SOI-film thickness and changes in the scattering mechanisms.

36 MATERIALS SCIENCE↗
DOE OSTI2017

Electron mobility in the inversion layers of fully depleted SOI films

The dependences of the electron mobility μ{sub eff} in the inversion layers of fully depleted double–gate silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) transistors on the density N{sub e} of induced charge carriers and temperature T are investigated at different states of the SOI film (inversion–accumulation) from the side of one of the gates. It is shown that at a high density of induced charge carriers of N{sub e} > 6 × 10{sup 12} cm{sup –2} the μeff(T) dependences allow the components of mobility μ{sub eff} that are related to scattering at surface phonons and from the film/insulator surface roughness to be distinguished. The μ{sub eff}(N{sub e}) dependences can be approximated by the power functions μ{sub eff}(N{sub e}) ∝ N{sub e}{sup −n}. The exponents n in the dependences and the dominant mechanisms of scattering of electrons induced near the interface between the SOI film and buried oxide are determined for different N{sub e} ranges and film states from the surface side.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Properties of HfLaO MOS capacitor deposited on SOI with plasma enhanced atomic layer deposition

Amorphous HfLaO dielectric film was successfully deposited on a silicon-on-insulator (SOI) substrate by plasma enhanced atomic layer deposition with in situ plasma treatment. The HfLaO film retained its insulating characteristics and is thermally stable even after annealing at 800 °C. The film has a dielectric constant of 27.3 and leakage of only 0.03 mA/cm{sup 2} at a gate bias of |Vg − V{sub fb}| = 1 V. The capacitance equivalent oxide thickness is 0.7 nm. A new parallel electrode testing structure was applied to measure C–V and J–V characteristics for the SOI samples. This testing method for metal–oxide–semiconductor capacitors has potential uses for measuring other layered substrates.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2015

Design and application of 8-channel SOI-based AWG demultiplexer for CWDM-system

Arrayed Waveguide Grating (AWG) serving as a demultiplexer (demux) has been designed on SOI platform and was utilized in a Coarse Wavelength Division Multiplexing (CWDM) system ranging from 1471 nm to 1611 nm. The investigation was carried out at device and system levels. At device level, 20 nm (∼ 2500 GHz) channel spacing was successfully simulated using beam propagation method (BPM) under TE mode polarization with a unique double S-shape pattern at arrays region. The performance of optical properties gave the low values of 0.96 dB dB for insertion loss and – 22.38 dB for optical crosstalk. AWG device was then successfully used as demultiplexer in CWDM system when 10 Gb/s data rate was applied in the system. Limitation of signal power due to attenuation and fiber dispersion detected by BER analyzer =10{sup −9} of the system was compared with theoretical value. Hence, the maximum distance of optical fiber can be achieved.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2015

Development of a CMOS Oscillator Chain for Particle Detection based on SOI technology

A new development of an oscillator concept, dedicated to the detection and tracking of particles with low fluxes, is presented. The solution is based on an indirect detection of the current generated at the input of the detection chain, through a Voltage Controlled Oscillator (VCO) response. The very first solution was proposed using bulk technology. This new development is based on SOI technology what makes it tolerant to radiations. (authors)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2015

Implementation of a Readout Circuit on SOI Technology for the Signal Conditioning of a Neutron Detector in Harsh Environment

A transistor level implementation of the analog block of a readout system on SOI process is presented here. This system is dedicated to the signal conditioning of a neutron detector in harsh environment. The different parts of the readout circuits are defined. The harsh environment constraints (crossing particle effect, high temperatures) are also detailed and modeled in the circuit in order to test and evaluate the characteristics of the designed block when working under these conditions. (authors)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Scalable free-space photonic antennas in foundry SOI silicon photonic platforms

We present a flexible, scalable, and low-noise design scheme for coupling free-space light into a silicon-on-insulator (SOI) electronic-photonic integrated circuit. The proposed scheme utilizes arrays of grating couplers with compact, inverse-designed power combining networks to couple a distributed optical collection area to a single output waveguide, forming a photonic antenna. Fabrication density compliance is maintained regardless of the antenna size, and the collection area can be scaled while maintaining a fixed noise floor. Using experimental grating array antennas fabricated in the GF45CLO platform, we demonstrate up to a 6.7× increase in the signal-to-noise ratio (SNR) of a lens-less monolithic free-space photonic receiver using a 4×4 grating array.

Rollinson, John (ORCID:0000000157130832)↗
DOE OSTI2016

Direct synthesis of ultrathin SOI structure by extremely low-energy oxygen implantation

We performed extremely low-energy {sup 16}O{sup +} implantation at 10 keV (R{sub p} ∼ 25 nm) followed by annealing aiming at directly synthesizing an ultrathin Si layer separated by a buried SiO{sub 2} layer in Si(001) substrates, and then investigated feasible condition of recrystallization and stabilization of the superficial Si and the buried oxide layer by significantly low temperature annealing. The elemental compositions were analyzed by Rutherford backscattering (RBS) and secondary ion mass spectroscopy (SIMS). The crystallinity of the superficial Si layer was quantitatively confirmed by ananlyzing RBS-channeling spectra. Cross-sectional morphologies and atomic configurations were observed by transmission electron microscope (TEM). As a result, we succeeded in directly synthesizing an ultrathin single-crystalline silicon layer with ≤20 nm thick separated by a thin buried stoichiometric SiO{sub 2} layer with ≤20 nm thick formed by extremely low-energy {sup 16}O{sup +} implantation followed by surprisingly low temperature annealing at 1050{sup ∘} C.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2019

SOI-MEMS Bulk Piezoresistive Displacement Sensor: A Comparative Study of Readout Circuits

Performance of several readout circuits, when applied to a MEMS-based bulk piezoresistive displacement sensor is compared in this study. The sensor comprises a pair of tilted clamped-guided silicon beams whose bulk piezoresistivity is used for displacement sensing. Wheatstone half-bridge, constant-voltage, and constant-current circuits are implemented to measure resistance changes of this sensor. We report full characterization of the sensor with these circuits and explore the sensor’s important characteristics such as linearity, bandwidth, and noise. The results reveal that the constant-current circuit provides the highest sensitivity at equal-power bias condition. Here, we find that the resolution of the sensor is degraded from 1.6 nm with the Wheatstone half-bridge and constant-voltage circuits to about 4.2 nm with the constant-current configuration. In the frequency domain, the sensor captures the full dynamics of the MEMS nanopositioner up to 20 kHz with all readout circuits.

42 ENGINEERING↗
DOE OSTI2017

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

This study presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 μm by 250 μm. The proof-of-concept receiver was implemented in an STMicroelectronics's 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a 4 × 4 subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables an efficient in-pixel A/D conversion. The per-pixel switched-capacitor ΔΣ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator's measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. Finally, the functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.

3-D photoacoustic (PA) imaging↗
DOE OSTI2021

Impact of Surface Recombination on Single-Event Charge Collection in an SOI Technology

Semiconductor–insulator interfaces play an important role in the reliability of integrated devices; however, the impact of these interfaces on the physical mechanisms related to single-event effects has not been previously reported. We present experimental data that demonstrate that single-event charge collection can be impacted by changes in interface quality. The experimental data, combined with simulations, show that single-event response may depend on surface recombination at interface defects. The effect depends on strike location and increases with increasing linear energy transfer (LET). Surface recombination can affect single-event charge collection for interfaces with a surface recombination velocity (SRV) of 1000 cm/s and is a dominant charge collection mechanism with SRV >10 5 cm/s.

42 ENGINEERING↗