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Single-stack InAs self-assembled quantum dots (QD) lasers based on InP substrate have been grown by metalorganic vapor phase epitaxy. The narrow ridge waveguide lasers lased up to 260 K in continuous wave operation, and near room temperature in pulsed mode, with wavelengths between 1.59 to 1.74 mu m.
Single-stack InAsSb self-assembled quantum-dot lasers based on (001) InP substrate have been grown by metalorganic vapor-phase epitaxy. The narrow ridge waveguide lasers lased at wavelengths near 2 mu m up to 25 degrees C in continuous-wave operation. At room temperature, a differential quantum efficiency of 13 percent is obtained and the maximum output optical power reaches 3 mW per facet with a threshold current density of 730 A/cm(sup 2). With increasing temperature the emission wavelength is extremely temperature stable, and a very low wavelength temperature sensitivity of 0.05 nm/degrees C is measured, which is even lower than that caused by the refractive index change.
Single-stack InAsSb self-assembled quantum-dot lasers based on (001) InP substrate have been grown by metalorganic vapor-phase epitaxy.
Packaging techniques for ultra high speed image processing were developed. These techniques involve the development of a signal feedthrough technique through LSI/VLSI sapphire substrates. This allows the stacking of LSI/VLSI circuit substrates in a 3 dimensional package with greatly reduced length of interconnecting lines between the LSI/VLSI circuits. The reduced parasitic capacitances results in higher LSI/VLSI computational speeds at significantly reduced power consumption levels.
AMTD partner Exelis developed & demonstrated a technique to manufacture a 400 mm thick substrate via stacking and fusing core structural elements to front and back faceplates; making a 40 cm cut-out of a 4 meter diameter 60 kilograms per square meter mirror. This new process offers a lower cost approach for manufacturing large-diameter high-stiffness mirrors.
The Advanced Mirror Technology Development (AMTD) project is in Phase 2 of a multiyear effort initiated in Fiscal Year (FY) 2012, to mature the Technology Readiness Level (TRL) of critical technologies required to enable 4-m-or-larger monolithic or segmented ultraviolet, optical, and infrared (UVOIR) space telescope primary-mirror assemblies for general astrophysics, ultra-high-contrast observations of exoplanets, and National Interest missions. Key accomplishments of 2016/17 include the completion of the Harris Corp approximately 150 Hz 1.5-meter Ultra-Low Expansion (ULE Registered trademark) mirror substrate using stacked core method to demonstrate lateral stability of the stacked core technology, as well as the characterization and validation by test of the mechanical and thermal performance of the 1.2-meter Zerodur (Registered trademark) mirror using the STOP model prediction and verification of CTE homogeneity.
A VHF microstrip patch antenna was developed to achieve a bandwidth of 45 MHz (30%) from 127 MHz to 172 MHz with dual-linear-polarization capability. This microstrip antenna used foam substrates and dual stacked patches with capacitive probe feeds to achieve wide bandwidth. Four such capacitive feeds were used to achieve dual polarizations with less than -20 dB of cross-polarization level. Twenty-four shorting pins were used on the lower patch to achieve acceptable isolation between the four feed probes. This antenna has a measured gain of 8.5 dB at 137 MHz and 10 dB at 162 MHz. By using the Method of Moments technique, multipath scattering patterns were calculated when the antenna is mounted on the outside of a Twin Otter aircraft.
Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.
We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit paths by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabricated parts were hybridized using a flip-chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.
We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit paths by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabricated parts were hybridized using a flip-chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.
We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit patbs by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabric.ted parts were hybridized using a Suss FCI50 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.
Miniaturization of electronic packages will play a key rule in future space avionics systems. Smaller avionics packages will reduce payloads while providing greater functionality for information processing and mission instrumentation. Current surface mount technology discrete passive devices not only take up significant space but also add weight. To that end, the use of embedded passive devices, such as capacitors, inductors and resistors will be instrumental in allowing electronics to be made smaller and lighter. Embedded passive devices fabricated on silicon or like substrates using thin film technology, promise great savings in circuit volume, as well as potentially improving electrical performance by decreasing parasitic losses. These devices exhibit a low physical profile and allow the circuit footprint to be reduced by stacking passive elements within a substrate. Thin film technologies used to deposit embedded passive devices are improving and costs associated with the process are decreasing.
Device approaches are investigated for optically addressed SLMs based on molecular-beam epitaxy (MBE) engineered III-V materials and structures. Strong photooptic effects can be achieved in periodically delta-doped multiple-quantum-well structures, but are still insufficient for high-contrast modulation with only single- or double-pass absorption through active layers of practical thickness. The asymmetric Fabry-Perot cavity approach is employed to permit extinction of light due to interference of light reflected from the front and back surfaces of the cavity. This approach is realized with an all-MBE-grown structure consisting of GaAs/AlAs quarter-wave stack reflector grown over the GaAs substrate as the high reflectance mirror and the GaAs surface as the low reflectance mirror. High-contrast modulation is achieved using a low-power InGaAs/GaAs quantum well laser for the control signal.
The commercial application of Indium Phosphide solar cells in practical space missions is crucially dependent upon achieving a major cost reduction which could be offered by heteroepitaxy on cheaper, more rugged substrates. Furthermore, significant mass reduction, compatibility with mechanically stacked multijunction cells, and elimination of the current loss through glue discoloration, is possible in III-V solar cells by the development of ultrathin, directly glassed cells. The progress of a UK collaborative program to develop high efficiency, homojunction InP solar cells, grown by MOCVD on Si substrates, is described. Results of homoepitaxial cells (is greater than 17 percent 1 Sun AM0) are presented, together with progress in achieving low dislocation density heteroepitaxy. Also, progress in a UK program to develop ultrathin directly-glassed GaAs cells is described. Ultrathin (5 micron) GaAs cells, with 1 Sun AM0 efficiencies up to 19.1 percent, are presented, together with progress in achieving a direct (adhesive-less) bond between the cell and coverglass. Consequential development to, for example, cell grids, are also discussed.
Single crystal SiC substrates were subjected to high-temperature H2/C3H8 gaseous etches. The etches resulted in a variety of surface features on 4H-SiC substrates that included elongated hillocks from 10 to more than 100 microns in length by a few microns in width. In some 4H- and 6H-SiC substrates, the etches resulted in a continuous coverage of macrosteps. We conclude that the morphology observed after the etching process is influenced by the local Si-C bilayer stacking sequence on the surface of off-(0001)oriented substrates. A model is presented for the formation of the hillocks, based on localized transformations of the 4H substrates during the high temperature etch process.
A multilayer dielectric device has been fabricated as a prototype of a low-loss, low-distortion, transmissive optical phase modulator that would provide as much as a full cycle of phase change for all frequency components of a transmitted optical pulse over a frequency band as wide as 6.3 THz. Arrays of devices like this one could be an alternative to the arrays of mechanically actuated phase-control optics (adaptive optics) that have heretofore been used to correct for wave-front distortions in highly precise optical systems. Potential applications for these high-speed wave-front-control arrays of devices include agile beam steering, optical communications, optical metrology, optical tracking and targeting, directional optical ranging, and interferometric astronomy. The device concept is based on the same principle as that of band-pass interference filters made of multiple dielectric layers with fractional-wavelength thicknesses, except that here there is an additional focus on obtaining the desired spectral phase profile in addition to the device s spectral transmission profile. The device includes a GaAs substrate, on which there is deposited a stack of GaAs layers alternating with AlAs layers, amounting to a total of 91 layers. The design thicknesses of the layers range from 10 nm to greater than 1 micrometer. The number of layers and the thickness of each layer were chosen in a computational optimization process in which the wavelength dependences of the indices of refraction of GaAs and AlAs were taken into account as the design was iterated to maximize the transmission and minimize the group-velocity dispersion for a wavelength band wide enough to include all significant spectral components of the pulsed optical signal to be phase modulated.
Systems and methods in accordance with embodiments of the invention proficiently produce carbon nanotube-based vacuum electronic devices. In one embodiment a method of fabricating a carbon nanotube-based vacuum electronic device includes: growing carbon nanotubes onto a substrate to form a cathode; assembling a stack that includes the cathode, an anode, and a first layer that includes an alignment slot; disposing a microsphere partially into the alignment slot during the assembling of the stack such that the microsphere protrudes from the alignment slot and can thereby separate the first layer from an adjacent layer; and encasing the stack in a vacuum sealed container.
We have demonstrated the hybridization of large mosaics of far-infrared detectors, joining separately fabricated sub-units into a single unit on a single, large substrate. We produced a single detector mockup on a 100mm diameter wafer and four mockup readout quadrant chips from a separate 100mm wafer. The individually fabricated parts were hybridized using a Suss FC150 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion (CTE) match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the mockup mosaic-hybridized detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently demonstrated.