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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Frontier system-on-chip (SoC) technology for microwave diagnostics (invited)

The next generation of fusion reactors, exemplified by projects such as the Demonstration Power Plant following the International Thermonuclear Experimental Reactor, faces the monumental challenge of proving the viability of generating electricity through thermonuclear fusion. This pursuit introduces heightened complexities in diagnostic methodologies, particularly in microwave-based diagnostics. The increased neutron fluence necessitates significant reductions in vessel penetrations and the elimination of internal diagnostics, posing substantial challenges. SoC technology offers a promising solution by enabling the miniaturization, modularization, integration, and enhancing the reliability of microwave systems. After seven years of research, our team successfully pioneered the V- and W-band system-on-chip approach, leading to the development of active transmitters and passive receiver modules applied in practical settings, notably within the DIII-D tokamak project. Arrays of these modules have supported microwave imaging diagnostics. New physics measurement results from the Electron Cyclotron Emission Imaging system on DIII-D provide compelling evidence of improved diagnostics following the adoption of SoC technology. Furthermore, we achieved a breakthrough in developing an F-band SoC, advancing higher frequency capabilities for fusion devices. These achievements represent a significant leap forward in fusion diagnostic technology, marking substantial progress toward establishing reliable and efficient plasma diagnostics for future fusion reactors.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2024

Internship Work Report

I worked on two projects during my summer internship at Sandia. My official title was “Intern - Mission Tech Electrical Eng./Computer Eng.- R&D Undergraduate Summer.” I worked at the central location, which is Albuquerque, New Mexico. The department you are placed in at Sandia doesn’t always correspond to the people you will be working with. For example, I only directly worked with one person from my department this summer. On one of my projects, I worked with a diverse team of engineers from many different departments. On my other project, I mainly worked with two departments, as the project had two distinct parts. As mentioned earlier, I worked on two projects during my summer at Sandia. The first project focused on a lightweight embedded controller in an advanced FPGA System-on-Chip for radar signal processing applications. The term “controller” refers to a hardware device that directs the flow of data between two entities. An FPGA is a reprogrammable integrated circuit (as opposed to an integrated circuit with one purpose). An FPGA was used on this project so in order to protype various ideas for our System-on-Chip. My role on the project was to implement designs on the fabric of the FPGA and design a state machine (written in C) for the processor. My second project was also heavily involved with embedded systems but had a different application. It focused on using a Newton-Raphson control algorithm to stabilize an inverted pendulum using a novel microcontroller. The pendulum dynamics were derived, and it was successfully simulated in MATLAB. I worked on integrating the microcontroller with the inverted pendulum machinery, and converting the Newton-Raphson control algorithm from MATLAB into C. The inverted pendulum was successfully stabilized using a simple PID controller and industry-standard microcontroller. The project is still ongoing, and the team is gearing up for more tests using the novel Newton-Raphson control algorithm and novel microcontroller

42 ENGINEERING↗
DOE OSTI2025

End-to-End Workflow for Machine-Learning-Based Qubit Readout With QICK and hls4ml

In this article, we present an end-to-end workflow for superconducting qubit readout that embeds codesigned neural networks into the quantum instrumentation control kit (QICK). Capitalizing on the custom firmware and software of the QICK platform, which is built on Xilinx radiofrequency system-on-chip field-programmable gate arrays (FPGAs), we aim to leverage machine learning (ML) to address critical challenges in qubit readout accuracy and scalability. The workflow utilizes the hls4ml package and employs quantization-aware training to translate ML models into hardware-efficient FPGA implementations via user-friendly Python application programming interfaces. We experimentally demonstrate the design, optimization, and integration of an ML algorithm for single transmon qubit readout, achieving 96% single-shot fidelity with a latency of 32.25 ns and less than 16% FPGA lookup table resource utilization. Our results offer the community an accessible workflow to advance ML-driven readout and adaptive control in quantum information processing applications.

42 ENGINEERING↗
DOE OSTI2025

Local Thermal Conductivity Patterning in Rotating Lattice Crystals of Anisotropic Sb 2 S 3

The ability to control material heat transport properties over space and time can drive advanced functionalities in thermal management for electronics and system-on-chip, and enable thermal circuits. Despite the technological relevance, there are limited demonstrations of local thermal property control. Rotating lattice single (RLS) crystals—formed via laser-induced crystallization of an amorphous substrate—offer a novel avenue for local crystal engineering, unlocking opportunities for microscale property patterning. Here, thermal conductivity (𝜅) imaging is applied to RLS crystals of Sb2S3 to resolve microscale 𝜅 variations across patterned regions. Amorphous areas exhibit 𝜅 as low as 0.6 Wm −1 K −1 , while crystalline regions display periodic 𝜅 variations from 0.7 to over 2.5 Wm −1 K −1 . These variations correspond to changes in crystal orientation, revealing marked 𝜅 anisotropy. The crystal out-of-plane direction (c axis)—featuring van der Waals bonds—shows amorphous-like transport, whereas in-plane directions (a, b axes) exhibit 3.5x and 1.7x larger 𝜅, respectively. First-principles calculations, in excellent agreement with experiments, suggest that the in-plane anisotropy originates from expressed Sb lone pairs, which impart a corrugation along the b axis affecting bond stiffness and 𝜅. These findings demonstrate microscale control of thermal properties via laser-processed metastructures, with significant implications for next-generation thermal management.

14 SOLAR ENERGY↗
DOE OSTI2024

Design of a 140 GHz waveguide notch filter for millimeter-wave receiver module protection in fusion plasma diagnostics

A carefully designed waveguide-based millimeter-wave notch filter, operating at 140 GHz, safeguards plasma diagnostic instruments from gyrotron leakage. Here, utilizing cylindrical cavity resonators with aperture coupling, the filter efficiently resonates 140 GHz wave-power into the TE 11p mode, optimizing various geometrical parameters for practical fabrication and high-yield production. Thorough thermal analysis ensures its ability to handle power. The filter achieves outstanding performance with over 90 dB rejection at 140 GHz while providing low insertion loss over the passband (110–138 GHz), which is ideally suited for system-on-chip approach F-band diagnostic system applications.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2025

A compact low-level RF control system for advanced concept compact electron linear accelerator

A compact low-level RF (LLRF) control system based on RF system-on-chip (RFSoC) technology has been designed for the Advanced Concept Compact Electron Linear-accelerator (ACCEL) program, which has challenging requirements in both RF performance and size, weight, and power consumption (SWaP). The compact LLRF solution employs the direct RF sampling technique of RFSoC, which samples the RF signals directly without any analog upconversion and downconversion. Compared with the conventional heterodyne based architecture used for the LLRF system of a linear accelerator (LINAC), the elimination of analog mixers can significantly reduce the size and weight of the system, especially with LINAC requiring a larger number of RF channels. Based on the requirements of ACCEL, a prototype LLRF platform has been developed, and the control schemes have been proposed. The prototype LLRF system demonstrated magnitude and phase fluctuation levels below 1% and 1° on the flattop of a 2 μs RF pulse. The LLRF control schemes proposed for ACCEL are implemented with a prototype hardware platform. In conclusion, this paper will introduce the new compact LLRF solution and summarize a selection of experimental test results of the prototype itself and with the accelerating structure cavities designed for ACCEL.

Liu, C. [SLAC National Accelerator Laboratory (SLA↗
DOE OSTI2023

Hardware design and testing of the generic rear transition module for the global trigger subsystem of ATLAS Phase-II Upgrade

Abstract In the framework of the ATLAS experiment’s Phase-II Upgrade at the High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 μs-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. The implementation of the functionality is firmware-focused and composed of several processing nodes, which are hosted on identical hardware, made up of an Advanced Telecommunications Computing Architecture (ATCA) front board, called Global Common Module (GCM), and a rear transition module (RTM), called Generic RTM (GRM). The GRM, which was developed to mitigate the risks deriving from the complex design and power management of the GCM, features an advanced Xilinx Versal Prime system-on-chip and can handle communication with the GCM and Front-End Link eXchange (FELIX) subsystem and trigger processors through 124 25.8 Gb/s transceiver links, for readout and control. Additionally, the GRM mounts a Low-Power GigaBit Transceiver (lpGBT) chip which enables emulation of the detector front-ends for integration tests. This paper presents the GRM hardware design and its testing.

Instruments & Instrumentation↗
DOE OSTI2024

GaN-based W-band receiver chip development for fusion plasma diagnostics

Millimeter-wave diagnostics have proven effective on various magnetic fusion devices worldwide, yet the formidable challenges posed by the harsh environments of future burning plasma devices, characterized by extreme temperatures, pressures, and radiation levels, remain a significant hurdle. To address these challenges, the utilization of wide bandgap Gallium Nitride (GaN)-based millimeter-wave diagnostics is a most promising solution for fusion reactor safety monitoring and control. A noteworthy W-band GaN-based system-on-chip receiver has been the demonstrated by employing HRL T3 40 nm GaN technology. This receiver chip, compactly designed with dimensions of 3 × 5 mm 2 , incorporates essential components such as the 75–110 GHz RF Low-Noise Amplifier (LNA), mixer, Intermediate Frequency (IF) amplifier, and Local Oscillator (LO) chain. This receiver chip will be packaged as a millimeter-wave receiver module and applied on the DIII-D National Fusion Facility, for fusion plasma edge shape monitoring for operational safety and dangerous disruption prediction. The laboratory measurement results have demonstrated suitable performance. Furthermore, this advancement is pivotal for accurate analysis of plasma behavior in the extreme conditions of burning plasma devices, driving progress in fusion research and technology.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2024

Performance evaluation of an RFSoC operating in a 1.25 Tesla magnetic field

Here, the Belle II experiment at the SuperKEKB collider is preparing for an upgrade after 2027–2028 to handle higher luminosity and increased background rates. A Radio Frequency System-on-Chip (RFSoC) has been identified as a potential candidate for a common front-end upgrade for subsystems requiring high-speed waveform digitization. The RFSoC's ADC and DAC channels were tested across various magnetic field strengths and a few different field orientations. Power consumption and boot memory functionality were also assessed. Results indicate stable operation with negligible performance degradation, suggesting the RFSoC's viability for high-speed digitization tasks in high magnetic field environments.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Accelerating Lossy and Lossless Compression on Emerging BlueField DPU Architectures

Data compression has become a crucial technique in addressing performance bottlenecks caused by increasing data volumes in High-Performance Computing (HPC), Big Data, and Deep Learning (DL). Despite its potential to boost system performance, recent studies have identified significant challenges with existing compression methods, mainly due to their high computational demands amidst continuously growing data sizes. Concurrently, the advent of Data Processing Units (DPUs), equipped with programmable System-on-Chip (SoC) and specialized compression accelerators, offers a promising opportunity to alter the landscape of data compression. This paper explores the complexities and potential of leveraging NVIDIA BlueField DPUs to accelerate lossy and lossless compression. Towards this, we introduce PEDAL, an innovative library that leverages the hardware capabilities of DPUs to unify and optimize data compression designs. Moreover, we seamlessly co-design PEDAL with the popular MPICH MPI library, demonstrating up to 101x speedup in compression time and 88x decrease in communication latency. Drawing on these achievements, we share our experience with various research communities about accelerating data compression on DPUs in communication-oriented HPC scenarios.

Li, Yuke↗
DOE OSTI2024

USPAS Digital Low-Level RF firmware and software suite (uspas_llrf) v1.0

The USPAS Digital Low-Level RF firmware and software suite was originally developed for the USPAS 2023 LLRF course, for demonstrating the close loop RF control on the BerkeleyLab Marble FPGA carrier and Zest digitizer platform in controlling the RF field for various accelerators. The suite features Register-transfer level (RTL) designs for the board-support layer, digital signal processing and verification test benches, system-on-chip architecture, and Experimental Physics and Industrial Control System (EPICS) support, utilizing a open-source tool chain.

Du, Qiang↗
DOE OSTI2025

Radio Frequency Field Programable Gate Array Implementation of Reflectometry Cable Monitoring

PNNL has developed an innovative cable testing system that leverages the Xilinx RF System-on-Chip (RFSoC) technology to create a more flexible and capable measurement tool than traditional approaches. The architecture is designed on the ZCU111 development board and takes advantage of the high-speed digital to analog converters (DAC) and analog to digital converters (ADC) to generate and capture digitally synthesized waveforms. The platform allows engineers to easily adjust power, frequency, duration and modulation on the fly rather than being locked into fixed hardware configurations

Tedeschi, Jonathan [Pacific Northwest National Lab↗
DOE OSTI2024

DIRECT RF SAMPLING BASED LLRF CONTROL SYSTEM FOR C-BAND LINEAR ACCELERATOR

Low Level RF (LLRF) control systems of linear accel- erators (LINACs) are typically implemented with hetero- dyne based architectures, which have complex analog RF mixers for up and down conversion. The Gen 3 Radio Fre- quency System-on-Chip (RFSoC) device from AMD Xilinx integrates data converters with maximum RF frequency of 6 GHz. This enables direct RF sampling of C-band LLRF signal typically operated at 5.712 GHz without any analogue mixers, which can significantly simplify the system architec- ture. The data converters sample RF signals in higher order Nyquist zones and then up or down convert digitally by the integrated data path in RFSoC. The closed-loop feedback control firmware implemented in FPGA integrated in RF- SoC can process the base-band signal from the ADC data path and calculate the updated phase and amplitude to be up- mixed by the DAC data path. We have developed a C-band LLRF control RFSoC platform with direct RF sampling, which targets Cool Copper Collider (𝐶3) and other C or S band LINAC research and development projects. In this paper, the architecture of the platform will be described. We have optimized the configuration of the data converter and characterized performance of them with RF pulses. The test results for some of the key performance parameters for the LLRF platform with our custom solid-state amplifier, such as phase and amplitude stability, will be discussed in this paper.

Liu, C↗
DOE OSTI2025

A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems

Domain-specific systems improve the performance of a specific set of applications compared to general-purpose processing systems by deploying custom hardware accelerators. These hardware accelerators are generated using high-level synthesis (HLS) tools. The HLS tools enable a comprehensive design space exploration to optimize the compute performance of the generated accelerators. However, they often ignore the challenges of implementing the accelerators in a system-on-chip, particularly how the accelerators access memory. Our work introduces a buffering system design that improves accelerators' memory accesses by intelligently employing burst transactions to prefetch useful data from external memory to on-chip local buffers. Our design is dynamic, parametric, and transparent to the accelerators generated by HLS tools. We derive the buffering system parameters using appropriate compiler-based analysis passes and memory channel latency constraints. The proposed buffering system design results in, on average, 8.8x performance improvements while lowering memory channel utilization on average by 53.2% for a set of PolyBench kernels.

Limaye, Ankur M. (ORCID:0000000194062584)↗
DOE OSTI2025

A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.

DAQ↗
DOE OSTI2025

A Study on the Impact of Temperature-Dependent Ferroelectric Switching Behavior in 3D Memory Architecture

The flourishing development of neural networks that require exponentially growing amounts of data has presented an elevated demand for memory footprint. To address this, researchers have been exploring hardware accelerators with innovative memory architectures like 3D memory. These 3D memory architectures offer enhanced storage capacity and processing capabilities, at a cost of rising on-chip temperature during operation. Hafnium Zirconium Oxide (HZO) based Ferroelectric Random Access Memory (FeRAM) is a promising nonvolatile memory candidate in neural network hardware accelerators for its outstanding write performance and reliability. However, its implementation in the architecture regarding the temperature-dependent ferroelectric switching behavior has not been well studied. In this work, we study the thermal impacts on polarization switching through experimental devices and simulation results. We conduct the circuit and architecture-level simulations to showcase that one can exploit this temperature rise to reduce FeRAM's write voltage and write energy due to its unique temperature-activated polarization switching mechanisms. As the on-chip temperature increases to 351K (ambient temperature at 300K) due to neural network workloads, the access energy per bit can be reduced by 27.6% when a dynamic write voltage is applied.

36 MATERIALS SCIENCE↗