Search NASA⌕ Search

SEARCH · Search NASA

Results for “threshold voltage”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2002

Minimum Arc Threshold Voltage Experiments on Extravehicular Mobility Unit Samples

The International Space Station (ISS) is now under construction in Low Earth Orbit (LEO). The process of building the ISS requires that astronauts carry out many Extravehicular Activities. To protect the astronauts form the hazardous space environment, they are required to wear a suit known as the Extravehicular Mobility Unit (EMU). For most Extra-Vehicular Activities (EVAs) the EMU is tethered to ISS via a steel safety tether. During the course of an EVA it is common for the safety tether to contact exposed metal on both the ISS and the EMU. In this case, the single point ground of the EMU would be at the same potential as the ISS with respect to the LEO Plasma. In the event that the metal structure of the ISS begins to charge negative of the plasma potential as a result of electron collection by the ISS photovoltaic arrays, then the EMU would also be driven to a negative potential. Anodized aluminum components on the EMU would then begin to develop a charge across their amortization layer as ions from the plasma are collected. In the case where large negative potentials are applied to the EMU, dielectric breakdown may occur as a large voltage difference is developed across the thin amortization layer (oxide). The resulting arc plasma may in turn couple to the charge accumulated on the nearby ISS anodized debris shields and thereby generate a large current flow through the metal EMU structure. Current flow through the EMU could result in an electrocution hazard for the Crew Member inside the EMU - and therefore represents an important safety concern. To address this concern, a series of experiments have been undertaken. In each experiment specially prepared anodized aluminum samples were placed in a LEO representative plasma and charged until dielectric breakdown occurred in the form of an arc. This process was repeated a number of times for three sets of samples. During each test the arc voltage and current were monitored. A statistical treatment of the arc voltage threshold will be presented. In addition, safe operating voltages for the EMU are suggested.

Schneider, Todd↗
NASA NTRS1998

Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub-0.1 (micron)meter MOSFET's: A 3-D 'Atomistic' Simulation Study

A three-dimensional (3-D) "atomistic" simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 microns MOSFET's is presented. For the first time a systematic analysis of random dopant effects down to an individual dopant level was carried out in 3-D on a scale sufficient to provide quantitative statistical predictions. Efficient algorithms based on a single multigrid solution of the Poisson equation followed by the solution of a simplified current continuity equation are used in the simulations. The effects of various MOSFET design parameters, including the channel length and width, oxide thickness and channel doping, on the threshold voltage lowering and fluctuations are studied using typical samples of 200 atomistically different MOSFET's. The atomistic results for the threshold voltage fluctuations were compared with two analytical models based on dopant number fluctuations. Although the analytical models predict the general trends in the threshold voltage fluctuations, they fail to describe quantitatively the magnitude of the fluctuations. The distribution of the atomistically calculated threshold voltage and its correlation with the number of dopants in the channel of the MOSFET's was analyzed based on a sample of 2500 microscopically different devices. The detailed analysis shows that the threshold voltage fluctuations are determined not only by the fluctuation in the dopant number, but also in the dopant position.

Asenov, Asen↗
NASA NTRS2000

Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

Asenov, Asen↗
NASA NTRS1999

Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1-(micron)meter MOSFET's with Epitaxial and (delta)-Doped Channels

A detailed three-dimensional (3-D) statistical 'atomistic' simulation study of fluctuation-resistant sub-0.1-(micron)meter MOSFET architectures with epitaxial channels and delta doping is presented. The need for enhancing the fluctuation resistance of the sub-0.1-(micron)meter generation transistors is highlighted by presenting summarized results from atomistic simulations of a wide range of conventional devices with uniformly doped channel. According to our atomistic results, the doping concentration dependence of the random dopant-induced threshold voltage fluctuations in conventional devices is stronger than the analytically predicted fourth-root dependence. As a result of this, the scaling of such devices will be restricted by the "intrinsic" random dopant-induced fluctuations earlier than anticipated. Our atomistic simulations confirm that the introduction of a thin epitaxial layer in the MOSFET's channel can efficiently suppress the random dopant-induced threshold voltage fluctuations in sub-0.1-(micron)meter devices. For the first time, we observe an "anomalous" reduction in the threshold voltage fluctuations with an increase in the doping concentration behind the epitaxial channel, which we attribute to screening effects. Also, for the first time we study the effect of a delta-doping, positioned behind the epitaxial layer, on the intrinsic threshold voltage fluctuations. Above a certain thickness of epitaxial layer, we observe a pronounced anomalous decrease in the threshold voltage fluctuation with the increase of the delta doping. This phenomenon, which is also associated with screening, enhances the importance of the delta doping in the design of properly scaled fluctuation-resistant sub-0.1-(micron)meter MOSFET's. Index Terms-Doping, fluctuations, MOSFET, semiconductor device simulation, silicon devices, threshold.

Asenov, Asen↗
NASA NTRS2000

Random Dopant Threshold Voltage Fluctuations in 50 nm Epitaxial Channel MOSFETs: A 3D 'Atomoc' Simulation Study

3D 'atomistic' simulations are used to study random dopant related threshold voltage fluctuations in 50 nm MOSFETs. Comparisons are made between conventionally doped transistors and transistors with thin epitaxial silicon layers on heavily doped silicon. Issues related to both the optimum threshold voltage control and the suppression of the threshold voltage dispersion are addressed.

Asenov, Asen↗
NASA NTRS1999

Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub 50 nm MOSFETs: a Statistical 3D 'Atomistic' Simulation Study

A 3D 'atomistic' simulation study of random dopant induced threshold voltage fluctuations and lowering in sub 50 nm MOSFETs is presented. The attention is focused mainly on devices with 30 nm effective channel length which represent the expected level of scaling at the end of the Silicon Roadmap. An efficient algorithm, based on a single 3D ap solution of the Poisson equation and a simplified current continuity equation, is used in the simulations. Large samples of microscopically different devices (typically 200) arc used in order to obtain statistically reliable results. The influence of different aspects of the conventional MOSFET design on the threshold voltage fluctuations and lowering are investigated. Results for fluctuation resistant device architectures based on low-doped epitaxial channel MOSFETs are also presented.

Asenov, Asen↗
NASA NTRS1999

Quantum Mechanical Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations and Lowering in Sub 0.1 Micron MOSFETs

A detailed study of the influence of quantum effects in the inversion layer on the random dopant induced threshold voltage fluctuations and lowering in sub 0.1 micron MOSFETs has been performed. This has been achieved using a full 3D implementation of the density gradient (DG) formalism incorporated in our previously published 3D 'atomistic' simulation approach. This results in a consistent, fully 3D, quantum mechanical picture which implies not only the vertical inversion layer quantisation but also the lateral confinement effects manifested by current filamentation in the 'valleys' of the random potential fluctuations. We have shown that the net result of including quantum mechanical effects, while considering statistical fluctuations, is an increase in both threshold voltage fluctuations and lowering.

Asenov, Asen↗
NASA NTRS2000

SNW 2000 Proceedings. Oxide Thickness Variation Induced Threshold Voltage Fluctuations in Decanano MOSFETs: a 3D Density Gradient Simulation Study

We use the density gradient (DG) simulation approach to study, in 3D, the effect of local oxide thickness fluctuations on the threshold voltage of decanano MOSFETs in a statistical manner. A description of the reconstruction procedure for the random 2D surfaces representing the 'atomistic' Si-SiO2 interface variations is presented. The procedure is based on power spectrum synthesis in the Fourier domain and can include either Gaussian or exponential spectra. The simulations show that threshold voltage variations induced by oxide thickness fluctuation become significant when the gate length of the devices become comparable to the correlation length of the fluctuations. The extent of quantum corrections in the simulations with respect to the classical case and the dependence of threshold variations on the oxide thickness are examined.

Asenov, Asen↗
NASA NTRS2000

Influence of the Polysilicon Gate on the Random Dopant Induced Threshold Voltage Fluctuations in Sub 100 nm MOSFETS with Thin Gate Oxides

In this paper for the first time we study the influence of the polysilicon gate on the random dopant induced threshold voltage fluctuations in sub 100 nm MOSFETs with tunnelling gate oxides. This is done by using an efficient 3D 'atomistic' simulation technique described elsewhere. Devices with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveale that the polysilicon gate is responsible for a substantial fraction of the threshold voltage fluctuations in both devices when the gate oxide is scaled to tunnelling thickness in the range of 1 - 2 nm.

Asenov, Asen↗
NASA NTRS1986

The voltage threshold for arcing for solar cells in LEO: Flight and ground test results

Ground and flight results of solar cell arcing in low Earth orbit (LEO) conditions are compared and interpreted. It is shown that an apparent voltage threshold for arcing may be produced by a strong power law dependence of arc rate on voltage, combined with a limited observation time. The change in this apparent threshold with plasma density is a reflection of the density dependence of the arc rate. A nearly linear dependence of arc rate on density is inferred from the data. A real voltage threshold for arcing for 2 by 2 cm solar cells may exist however, independent of plasma density, near -230 V relative to the plasma. Here, arc rates may change by more than an order of magnitude for a change of only 30 V in array potential. For 5.9 by 5.9 solar cells, the voltage dependence of the arc rate is steeper, and the data are insufficient to indicate the existence of an arcing increased by an atomic oxygen plasma, as is found in LEO, and by arcing from the backs of welded-through substrates.

Ferguson, D. C.↗
NASA NTRS1986

The voltage threshold for arcing for solar cells in Leo - Flight and ground test results

Ground and flight results of solar cell arcing in low earth orbit (LEO) conditions are compared and interpreted. It is shown that an apparent voltage threshold for arcing may be produced by a storage power law dependence of arc rate on voltage, combined with a limited observation time. The change in this apparent threshold with plasma density is a reflection of the density dependence of the arc rate. A nearly linear dependence of arc rate on density is inferred from the data. A real voltage threshold for arcing for 2 by 2 cm solar cells may exist however, independent of plasma density, near -230 V relative to the plasma. Here, arc rates may change by more than an order of magnitude for a change of only 30 V in array potential. For 5.9 by 5.9 solar cells, the voltage dependence of the arc rate is steeper, and the data are insufficient to indicate the existence of an arcing increased by an atomic oxygen plasma, as is found in LEO, and by arcing from the backs of welded-through substrates.

Ferguson, Dale C.↗
NASA NTRS1998

Efficient 3D 'Atomistic' Simulation Technique for Studying of Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Decanano MOSFETs

A 3D 'atomistic' simulation technique to study random dopant induced threshold voltage lowering and fluctuations in sub 0.1 micron MOSFETs is presented. It allows statistical analysis of random impurity effects down to the individual impurity level. Efficient algorithms based on a single solution of Poisson's equation, followed by the solution of a simplified current continuity equation are used in the simulations.

Asenov, Asen↗
NASA NTRS2000

Effect of Oxide Interface Roughness on the Threshold Voltage Fluctuations in Decanano MOSFETs with Ultrathin Gate Oxides

In this paper we use the Density Gradient (DG) simulation approach to study, in 3-D, the effect of local oxide thickness fluctuations on the threshold voltage of decanano MOSFETs on a statistical scale. The random 2-D surfaces used to represent the interface are constructed using the standard assumptions for the auto-correlation function of the interface. The importance of the Quantum Mechanical effects when studying oxide thickness fluctuations are illustrated in several simulation examples.

Asenov, Asen↗
NASA NTRS1990

Threshold voltage for arcing on negatively biased solar arrays

The arcing that has been found to occur when negatively biased high-voltage solar arrays in LEO lie at a critical voltage with respect to the plasma environment is presently proposed to be due to a breakdown of gas emitted under electron bombardment from the solar cells' cover-glass. The elements of the model for this phenomenon include an electron current flow from the interconnect to a neighboring cover-glass, which desorbs neutral molecules under the electron bombardment. The neutral molecules form a gas over the interconnect, and this gas breaks down when the voltage over the interconnect is sufficiently high. Specific scaling predictions are made on the basis of the geometric structure and gas in question.

Hastings, Daniel E.↗
NASA NTRS2010

SONOS Nonvolatile Memory Cell Programming Characteristics

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization. The characterization of the SONOS memory cell predicted by the model closely agrees with experimental data obtained from actual SONOS memory cells. The tunnel current, drain current, threshold voltage and read drain current all closely agreed with empirical data.

MacLeod, Todd C.↗
NASA NTRSDate not supplied

Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

We compare the failure mechanism and performance of a silicon carbide (SiC) semi-superjunction (semi-SJ) power DMOSFET against pure SJ and conventional DMOSFET when struck by a single heavy ion. The Single-Event Burnout (SEB) failure mechanism was identified as the thermal runaway from second breakdown resulting in mesoplasma formation. The semi-SJ design shifts the mesoplasma location from the drift/substrate interface seen in the control device structures to a location along the center of the P-pillar and closer towards the DMOSFET surface, thus significantly improving the SEB threshold voltage. The SEB threshold voltage varies with pillar width and ratio of pillar thickness to drift layer thickness. A maximum value of SEB threshold voltage is reached when the pillar to drift layer ratio is 0.9 and the pillar width is 2.4 μm. The semi-SJ SEB/breakdown voltage ratio is 100% and 13% higher than the pure SJ and conventional DMOSFET, respectively. Using a new figure of merit (FOM), which accounts for the tradeoff between SEB threshold voltage and on-state performance, we find that the SiC semi-SJ DMOSFET achieves a FOM that is 1.8 and 8 times higher than SJ and conventional DMOSFET, respectively, making the semi-SJ a competitive candidate for radiation hardened applications.

SiC↗
NASA NTRS2003

Radiation tolerant back biased CMOS VLSI

A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

Maki, Gary K.↗