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Results for “transistor scaling”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

On-Chip Batteries as Distributed Energy Sources in Heterogeneous 2.5D/3D Integrated Circuits

Energy efficiency in digital systems faces challenges due to the constraints imposed by small-scale transistors. Moreover, the growing demand for portable consumer electronics necessitates the use of compact energy sources. To address these challenges, heterogeneous 3D IC technology has emerged as a promising solution for the former. Regarding the latter, we propose the concept of distributed batteries within a heterogeneous 3D IC. This approach involves utilizing multiple smaller batteries with different specifications among different modules of 3D ICs. This approach optimizes performance and overcomes limitations associated with both 3D ICs and conventional power delivery methods. Distributed batteries play a vital role in effectively managing the heat generated by energy sources and modules within a 3D IC. Furthermore, they contribute to achieving a uniform distribution of heat throughout the entire structure, which ultimately ensures the optimal performance of the batteries and modules. The simulation results indicate a 40 percent enhancement in achieving a more even distribution of generated heat. Additionally, the proposed distributed battery techniques improve power delivery, enhance reliability, and enable optimized voltage regulation while improving efficiency. In addition to the primary benefits, alternative configurations of the proposed approach can offer extra energy storage capacity and act as efficient electromagnetic shields, resulting in an impressive reduction of external electromagnetic noises by 60 dB.

47 OTHER INSTRUMENTATION↗
NASA NTRS2004

Pass-transistor very large scale integration

Logic elements are provided that permit reductions in layout size and avoidance of hazards. Such logic elements may be included in libraries of logic cells. A logical function to be implemented by the logic element is decomposed about logical variables to identify factors corresponding to combinations of the logical variables and their complements. A pass transistor network is provided for implementing the pass network function in accordance with this decomposition. The pass transistor network includes ordered arrangements of pass transistors that correspond to the combinations of variables and complements resulting from the logical decomposition. The logic elements may act as selection circuits and be integrated with memory and buffer elements.

Maki, Gary K.↗
DOE OSTI2022

Ultrathin ferroic HfO 2 –ZrO 2 superlattice gate stack for advanced transistors

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO 2 , which remains the material of choice to date. Here we report HfO 2 –ZrO 2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric–antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal–oxide–semiconductor capacitors is equivalent to an effective SiO 2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO 2 -based high-dielectric-constant gate stacks without scavenging the interfacial SiO 2 , which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO 2 –ZrO 2 multilayers, stabilized with competing ferroelectric–antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO 2 -based high-dielectric-constant materials.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Low-temperature processed beta-phase In 2 Se 3 ferroelectric semiconductor thin film transistors

As scaling becomes increasingly difficult, there is growing interest in vertical or three-dimensional stacking of transistors and especially memory. Ferroelectric semiconductor field effect transistors can be key enablers to improve energy efficiency and overall chip and memory performance. In this work, low-temperature processed, back-end-of-the-line compatible transistors were demonstrated by depositing a layered chalcogenide ferroelectric semiconductor, beta-phase In 2 Se 3 , at temperature as low as 400 °C. Top gate n-channel In 2 Se 3 thin film transistors were fabricated with field-effect mobility ∼1 cm 2 V −1 s −1 , and simple polarization switching based memory results are presented.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Ultra‐Steep Slope Impact Ionization Transistors Based on Graphene/InAs Heterostructures

With the continued scaling of transistors, there is a growing trend for developing steep slope transistors with subthreshold swing (SS) below Boltzmann limitation ( k T/ q ). To this end, impact ionization metal oxide semiconductor (I‐MOS) transistors are attractive for a unique combination of high ON‐state current density, small hysteresis, and ultra‐steep SS slope. However, the performance of I‐MOS is generally limited by the relatively thick depletion region and large operation voltage required for the activation of impact ionization (typically >5 V). Herein, a high‐performance I‐MOS is constructed by van der Waals integrating single‐crystal InAs film with graphene. Due to the low bandgap of InAs as well as the semi‐metallic nature of graphene, the InAs/graphene I‐MOS demonstrates a low operation voltage of 1.5 V, high ON‐state current of 230 μA μm −1 , steep SS <0.6 mV dec −1 , and large ON–OFF ratio >10 6 at temperature below 200 K. Furthermore, a negative transconductance and steep current oscillation is observed in the subthreshold regime, and a device working mechanism is proposed for this novel phenomenon. This study not only pushes the performance limit of I‐MOS but also defines a general pathway to van der Waals heterostructures between conventional III–V compound semiconductors and novel 2D materials for unconventional device functions.

Liu, Yuan↗
DOE OSTI2023

Hybrid stochastic synapses enabled by scaled ferroelectric field-effect transistors

Achieving brain-like density and performance in neuromorphic computers necessitates scaling down the size of nanodevices emulating neuro-synaptic functionalities. However, scaling nanodevices results in reduction of programming resolution and emergence of stochastic non-idealities. While prior work has mainly focused on binary transitions, in this work, we leverage the stochastic switching of a three-state ferroelectric field-effect transistor to implement a long-term and short-term two-tier stochastic synaptic memory with a single device. Experimental measurements are performed on a scaled 28 nm high-k metal gate technology-based device to develop a probabilistic model of the hybrid stochastic synapse. In addition to the advantage of ultra-low programming energies afforded by scaling, our hardware–algorithm co-design analysis reveals the efficacy of the two-tier memory in comparison to binary stochastic synapses in on-chip learning tasks—paving the way for algorithms exploiting multi-state devices with probabilistic transitions beyond deterministic ones.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
NASA NTRS2003

Scaling and Single Event Effects (SEE) Sensitivity

This paper begins by discussing the potential for scaling down transistors and other components to fit more of them on chips in order to increasing computer processing speed. It also addresses technical challenges to further scaling. Components have been scaled down enough to allow single particles to have an effect, known as a Single Event Effect (SEE). This paper explores the relationship between scaling and the following SEEs: Single Event Upsets (SEU) on DRAMs and SRAMs, Latch-up, Snap-back, Single Event Burnout (SEB), Single Event Gate Rupture (SEGR), and Ion-induced soft breakdown (SBD).

Oldham, Timothy R.↗
NASA NTRS2005

Impact of Device Scaling on Deep Sub-micron Transistor Reliability: A Study of Reliability Trends using SRAM

As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.

CMOS integrated circuits↗
DOE OSTI2021

Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on the Device Variation of Ferroelectric FET

In this work, a comprehensive study of random spatial fluctuation of the ferroelectric (FE) phase and dielectric (DE) phase in FeFETs is conducted to understand its impact on device variation. It is found that: i) there exists a certain DE percentage threshold that below which the increase of the DE phase does not significantly impact the device memory window and variation and only above which evident device degradation can be observed; ii) increasing the DE phase increases the variation in the memory window and the coercive field distribution further exacerbates the variation, hence degrading the sensing margin; iii) decreasing the number of grains degrades the device variation, which calls for further grain size engineering for variation suppression.

42 ENGINEERING↗
DOE OSTI2020

Advanced CMOS Reliability Update: Sub 20nm FinFET Assessment

Advances in FinFET design and fabrication enable manufacturing of denser, more compact integrated circuits (ICs) with substantially reduced leakage while shortening the channel-lengths. The same stress-induced leakage and breakdown degradation mechanisms that affect planar transistors also impact FinFET devices. Reliability concerns such as Bias Temperature Instability (BTI), Time Dependent Dielectric Breakdown (TDDB), and Hot Carrier Injection (HCI) become very important with changes to transistor geometry and fin sidewall crystal orientation. Recent testing has shown that FinFETs respond differently to radiation (radiation effects such as total ionizing dose) when compared to planar transistors. These reliability and radiation effects issues become very important when changing transistor geometry and scaling FinFETs towards smaller feature sizes (22-nm, 16-nm, 14- nm, 10-nm, and smaller critical dimensions). The comparable 2019 state of the art transistor densities in current high-volume manufacturing silicon-based foundries is 7-nm (ISMC, Samsung) and 10-nm (Intel) [www.anandtech.com,fuse.wikichip.org]. Released products include supporting components for the cellphone and commercial microprocessor markets respectively. Extensive development in the foundry industry is driving to a 5-nm technology node in late 2020.

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

The future of computing beyond Moore’s Law

Moore’s Law is a techno-economic model that has enabled the information technology industry to double the performance and functionality of digital electronics roughly every 2 years within a fixed cost, power and area. Advances in silicon lithography have enabled this exponential miniaturization of electronics, but, as transistors reach atomic scale and fabrication costs continue to rise, the classical technological driver that has underpinned Moore’s Law for 50 years is failing and is anticipated to flatten by 2025. Here, this article provides an updated view of what a post-exascale system will look like and the challenges ahead, based on our most recent understanding of technology roadmaps. It also discusses the tapering of historical improvements, and how it affects options available to continue scaling of successors to the first exascale machine. Lastly, this article covers the many different opportunities and strategies available to continue computing performance improvements in the absence of historical technology drivers. This article is part of a discussion meeting issue ‘Numerical algorithms for high-performance computational science’.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1979

Standard Transistor Array (STAR). Volume 1: Placement technique

A large scale integration (LSI) technology, the standard transistor array uses a prefabricated understructure of transistors and a comprehensive library of digital logic cells to allow efficient fabrication of semicustom digital LSI circuits. The cell placement technique for this technology involves formation of a one dimensional cell layout and "folding" of the one dimensional placement onto the chip. It was found that, by use of various folding methods, high quality chip layouts can be achieved. Methods developed to measure of the "goodness" of the generated placements include efficient means for estimating channel usage requirements and for via counting. The placement and rating techniques were incorporated into a placement program (CAPSTAR). By means of repetitive use of the folding methods and simple placement improvement strategies, this program provides near optimum placements in a reasonable amount of time. The program was tested on several typical LSI circuits to provide performance comparisons both with respect to input parameters and with respect to the performance of other placement techniques. The results of this testing indicate that near optimum placements can be achieved by use of the procedures incurring severe time penalties.

Cox, G. W.↗
NASA NTRS2008

Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C

The fabrication and testing of the first semiconductor transistors and small-scale integrated circuits (ICs) to achieve up to 3000 h of stable electrical operation at 500 C in air ambient is reported. These devices are based on an epitaxial 6H-SiC junction field-effect transistor process that successfully integrated high temperature ohmic contacts, dielectric passivation, and ceramic packaging. Important device and circuit parameters exhibited less than 10% of change over the course of the 500 C operational testing. These results establish a new technology foundation for realizing durable 500 C ICs for combustion-engine sensing and control, deep-well drilling, and other harsh-environment applications.

Neudeck, Philip G.↗
DOE OSTI2023

Scaling and statistics of bottom-up synthesized armchair graphene nanoribbon transistors

Bottom-up assembled nanomaterials and nanostructures allow for the studies of rich and unprecedented quantum-related and mesoscopic transport phenomena. However, it can be difficult to quantify the correlations between the geometrical or structural parameters obtained from advanced microscopy and measured electrical characteristics when they are made into macroscopic devices. Here, we propose a strategy to connect the nanomaterial morphologies and the device performance through a Monte Carlo device model and apply it to understand the scaling trends of bottom-up synthesized armchair graphene nanoribbon (GNR) transistors. A new nanofabrication process is developed for GNR transistors with channel length down to 7 nm. Further, the impacts of the GNR spatial distributions and the device geometries on the device performance are investigated systematically through comparison of experimental data with the model. Through this study, challenges and opportunities of transistor technologies based on bottom-up synthesized GNRs are pinpointed, paving the way to the further improvement of the GNR device performance for future transistor technology nodes.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Record high room temperature resistance switching in ferroelectric-gated Mott transistors unlocked by interfacial charge engineering

Abstract The superior size and power scaling potential of ferroelectric-gated Mott transistors makes them promising building blocks for developing energy-efficient memory and logic applications in the post-Moore’s Law era. The close to metallic carrier density in the Mott channel, however, imposes the bottleneck for achieving substantial field effect modulation via a solid-state gate. Previous studies have focused on optimizing the thickness, charge mobility, and carrier density of single-layer correlated channels, which have only led to moderate resistance switching at room temperature. Here, we report a record high nonvolatile resistance switching ratio of 38,440% at 300 K in a prototype Mott transistor consisting of a ferroelectric PbZr 0.2 Ti 0.8 O 3 gate and an R NiO 3 ( R : rare earth)/La 0.67 Sr 0.33 MnO 3 composite channel. The ultrathin La 0.67 Sr 0.33 MnO 3 buffer layer not only tailors the carrier density profile in R NiO 3 through interfacial charge transfer, as corroborated by first-principles calculations, but also provides an extended screening layer that reduces the depolarization effect in the ferroelectric gate. Our study points to an effective material strategy for the functional design of complex oxide heterointerfaces that harnesses the competing roles of charge in field effect screening and ferroelectric depolarization effects.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2022

Atomic-scale defects generated in the early/intermediate stages of dielectric breakdown in Si/SiO 2 transistors

In this study, electrically detected magnetic resonance and near-zero-field magnetoresistance measurements were used to study atomic-scale traps generated during high-field gate stressing in Si/SiO 2 MOSFETs. The defects observed are almost certainly important to time-dependent dielectric breakdown. The measurements were made with spin-dependent recombination current involving defects at and near the Si/SiO 2 boundary. The interface traps observed are P b0 and P b1 centers, which are silicon dangling bond defects. The ratio of P b0 /P b1 is dependent on the gate stressing polarity. Electrically detected magnetic resonance measurements also reveal generation of E' oxide defects near the Si/SiO 2 interface. Near-zero-field magnetoresistance measurements made throughout stressing reveal that the local hyperfine environment of the interface traps changes with stressing time; these changes are almost certainly due to the redistribution of hydrogen near the interface.

42 ENGINEERING↗
DOE OSTI2024

Variation-Resilient FeFET-Based In-Memory Computing Leveraging Probabilistic Deep Learning

Reliability issues stemming from device level nonidealities of nonvolatile emerging technologies like ferroelectric field-effect transistors (FeFETs), especially at scaled dimensions, cause substantial degradation in the accuracy of in-memory crossbar-based AI systems. Here, in this work, we present a variation-aware design technique to characterize the device level variations and to mitigate their impact on hardware accuracy employing a Bayesian neural network (BNN) approach. An effective conductance variation model is derived from the experimental measurements of cycle-to-cycle (C2C) and device-to-device (D2D) variations performed on FeFET devices fabricated using 28 nm high-k metal gate technology. The variations were found to be a function of different conductance states within the given programming range, which sharply contrasts earlier efforts where a fixed variation dispersion was considered for all conductance values. Such variation characteristics formulated for three different device sizes at different read voltages were provided as prior variation information to the BNN to yield a more exact and reliable inference. Near-ideal accuracy for shallow networks (MLP5 and LeNet models) on the MNIST dataset and limited accuracy decline by ~3.8%–16.1% for deeper AlexNet models on CIFAR10 dataset under a wide range of variations corresponding to different device sizes and read voltages, demonstrates the efficacy of our proposed device-algorithm co-design technique.

97 MATHEMATICS AND COMPUTING↗