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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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11 records

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NASA NTRS1979

Implementing a bubble memory hierarchy system

This paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.

Segura, R.↗

NASA NTRS1989

The FORCE - A highly portable parallel programming language

This paper explains why the FORCE parallel programming language is easily portable among six different shared-memory multiprocessors, and how a two-level macro preprocessor makes it possible to hide low-level machine dependencies and to build machine-independent high-level constructs on top of them. These FORCE constructs make it possible to write portable parallel programs largely independent of the number of processes and the specific shared-memory multiprocessor executing them.

Jordan, Harry F.↗

NASA NTRS1989

The FORCE: A highly portable parallel programming language

Here, it is explained why the FORCE parallel programming language is easily portable among six different shared-memory microprocessors, and how a two-level macro preprocessor makes it possible to hide low level machine dependencies and to build machine-independent high level constructs on top of them. These FORCE constructs make it possible to write portable parallel programs largely independent of the number of processes and the specific shared memory multiprocessor executing them.

Jordan, Harry F.↗

NASA NTRS1989

Parallel Optical Random Access Memory (PORAM)

It is shown that the need to minimize component count, power and size, and to maximize packing density require a parallel optical random access memory to be designed in a two-level hierarchy: a modular level and an interconnect level. Three module designs are proposed, in the order of research and development requirements. The first uses state-of-the-art components, including individually addressed laser diode arrays, acousto-optic (AO) deflectors and magneto-optic (MO) storage medium, aimed at moderate size, moderate power, and high packing density. The next design level uses an electron-trapping (ET) medium to reduce optical power requirements. The third design uses a beam-steering grating surface emitter (GSE) array to reduce size further and minimize the number of components.

Alphonse, G. A.↗

NASA NTRS2000

Parallel performance investigations of an unstructured mesh Navier-Stokes solver

A Reynolds-averaged Navier-Stokes solver based on unstructured mesh techniques for analysis of high-lift configurations is described. The method makes use of an agglomeration multigrid solver for convergence acceleration. Implicit line-smoothing is employed to relieve the stiffness associated with highly stretched meshes. A GMRES technique is also implemented to speed convergence at the expense of additional memory usage. The solver is cache efficient and fully vectorizable, and is parallelized using a two-level hybrid MPI-OpenMP implementation suitable for shared and/or distributed memory architectures, as well as clusters of shared memory machines. Convergence and scalability results are illustrated for various high-lift cases.

Mavriplis, Dimitri J.↗

NASA NTRS1976

Magnetoresistance and noise properties of chevron stretcher detectors for field access bubble domain devices

Experiments were devised to study the angular variation of the resistance and noise properties of one- and two-level chevron stretcher magnetoresistive detectors for use in field access bubble memory devices. All measurements, made with an electronic system, were performed on glass or garnet samples upon which 1 micron of SiO2 was sputter-deposited, followed by 4000 A of Permalloy for the 28-micron-period devices and 0.8 microns of SiO2, followed by 3000 A of Permalloy for the 20-micron-period devices. The geometrical and drive-state dependence of the zero-state noise were studied, as was its frequency dependence. It is found that both types of detectors operate primarily in the amplitude-shift mode for drive fields of interest and that the presence of a bubble in a detector causes a magnetoresistance change equal to that produced by increasing the in-plane drive field about 8 Oe in the absence of a bubble.

George, P. K.↗

NASA NTRS1981

Common data buffer

Time-shared interface speeds data processing in distributed computer network. Two-level high-speed scanning approach routes information to buffer, portion of which is reserved for series of "first-in, first-out" memory stacks. Buffer address structure and memory are protected from noise or failed components by error correcting code. System is applicable to any computer or processing language.

Byrne, F.↗

NASA NTRS1992

Persistence and predictability in a perfect model

A realistic two-level GCM is used to examine the relationship between predictability and persistence. Predictability is measured by the average divergence of ensembles of solutions starting from perturbed initial conditions, and persistence is defined in terms of the autocorrelation function based on a single long-term model integration. The average skill of the dynamical forecasts is compared with the skill of simple persistence-based statistical forecasts. For initial errors comparable in magnitude to present-day analysis errors, the statistical forecast loses all skill after about one week, reflecting the lifetime of the lowest frequency fluctuations in the model. Large ensemble mean dynamical forecasts would be expected to remain skillful for about 3 wk. The disparity between the skill of the statistical and dynamical forecasts is greater for the higher frequency modes, which have little memory beyond 1 d, yet remain predictable for about 2 wk. The results are analyzed in terms of two characteristic time scales.

Schubert, Siegfried D.↗

NASA NTRS1996

Parallel Newton-Krylov-Schwarz algorithms for the transonic full potential equation

We study parallel two-level overlapping Schwarz algorithms for solving nonlinear finite element problems, in particular, for the full potential equation of aerodynamics discretized in two dimensions with bilinear elements. The overall algorithm, Newton-Krylov-Schwarz (NKS), employs an inexact finite-difference Newton method and a Krylov space iterative method, with a two-level overlapping Schwarz method as a preconditioner. We demonstrate that NKS, combined with a density upwinding continuation strategy for problems with weak shocks, is robust and, economical for this class of mixed elliptic-hyperbolic nonlinear partial differential equations, with proper specification of several parameters. We study upwinding parameters, inner convergence tolerance, coarse grid density, subdomain overlap, and the level of fill-in in the incomplete factorization, and report their effect on numerical convergence rate, overall execution time, and parallel efficiency on a distributed-memory parallel computer.

Cai, Xiao-Chuan↗

NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.

Silicon Carbide↗

NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 µm to 2 µm) coupled with enlarged die size (from 3 x 3 mm to 5 x 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

silicon carbide↗