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This presentation gives the status of theoretical and experimental efforts at JPL, in the development of environmentally robust (rad hard and rad tolerant), ultra-low power, high performance cmos active pixel sensor (aps) imagers for star tracker/imager applications.
This paper gives the status of theoretical and experimental efforts at JPL in the development of environmentally robust (radiation hard and radiation tolerant), ultra-low power, high performance CMOS active pixel sensor (APS) imagers for star tracker/imager applications.
A low-power high-speed smart sensor system based on a large format active pixel sensor (APS) integrated with a programmable neural processor for space exploration missions is presented. The concept of building an advanced smart sensing system is demonstrated by a system-level microchip design that is composed with an APS sensor, a programmable neural processor, and an embedded microprocessor in a SOI CMOS technology. This ultra-fast smart sensor system-on-a-chip design mimics what is inherent in biological vision systems. Moreover, it is programmable and capable of performing ultra-fast machine vision processing in all levels such as image acquisition, image fusion, image analysis, scene interpretation, and control functions. The system provides about one tera-operation-per-second computing power which is a two order-of-magnitude increase over that of state-of-the-art microcomputers. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and advanced VLSI system-on-a-chip implementation.