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Results for “ultra-low power (ULP)”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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A 194nW Energy-Performance-Aware loT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization

A self-powered IoT system-on-chip (SoC) reduces power to sub-μw and employs multiple power-management techniques to trade-off ultra-low power (ULP), higher performance, smaller energy harvester footprint, and longer operating lifetime. Minimum Energy Point Tracking (MEPT) [1]–[4] keeps an SoC operating at the minimum energy point (MEP) to enhance system lifetime. Previous sample-and-hold MEPT schemes need frequent voltage comparisons and a high-frequency clock that increases power [2]. Current-ratio-based MEPT relies on specialized CMOS technology for body-bias tuning [3]. A switched-capacitor-based MEPT can achieve energy minimization at a targeted performance [4], but it uses a 30MHz clock witμW power consumption and low power efficiency. For ULP IoT applications, SoCs need to have ultra-low quiescent power, high efficiency for energy delivery, performance scaling based on available energy, and energy minimization to increase system lifetime. In this work, we propose an ULP IoT SoC with a triple-mode power management unit (PMU) that integrates energy-performance scaling, event-driven fast DVFS, and MEPT features to improve the system energy efficiency, as shown in Fig. 13.8.1. This work achieves a minimum 194nW power consumption for the SoC and 5.2nW quiescent power for the PMU with a 92.6% peak efficiency and >10 4 dynamic range. The timing waveform in Fig. 13.8.1 (bottom), demonstrates the transition of the three modes including energy aware (EA), performance aware (PA), and MEPT based on event priority and input voltage level which reflects the energy availability. As such, the system energy consumption and performance could be well-balanced based on both the input and output conditions.

self-powered IoT system-on-chip (SoC)↗

Reliability Considerations of ULP Scaled CMOS in Spacecraft Systems

NASA, the aerospace community, and other high reliability (hi-rel) users of advanced microelectronic products face many challenges as technology continues to scale into the deep sub-micron region. Decreasing the feature size of CMOS devices not only allows more components to be placed on a single chip, but it increases performance by allowing faster switching (or clock) speeds with reduced power compared to larger scaled devices. Higher performance, and lower operating and stand-by power characteristics of Ultra-Low Power (ULP) microelectronics are not only desirable, but also necessary to meet low power consumption design goals of critical spacecraft systems. The integration of these components in such systems, however, must be balanced with the overall risk tolerance of the project.

reliability↗

An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction

This paper presents an ultra-low power (ULP) node-controlling system-on-chip (SoC) used for power-mode management and phantom energy reduction of miscellaneous electric loads (MELs). The SoC is powered from a single 2.5 V voltage supply enabled by the integrated power management unit (PMU) and can control up to 16 MELs due to the on-chip 16-channel correlator and the 32b RISC-V microprocessor. To further reduce the system power consumption, two clock domains have been adopted for the correlator and the processor separately. Fabricated in 65-nm CMOS, the measured minimum power consumption of the proposed SoC is only 85 nW at 0.45 V voltage supply and 1 kHz clock frequency. The measured maximum operating frequency can go up to 148 kHz with a 0.55 V supply. An application experiment successfully demonstrates that the SoC controls the power modes of MELs from wake-up to cut-off to save the average power and phantom energy.

power-mode management, phantom energy, phantom pow↗

Improving Energy Efficiency of Wireless Communication Circuitry in Miscellaneous Electric Loads (Final Report)

The overarching objective of this project is to reduce phantom power in miscellaneous electric loads (MELs). We achieve this power reduction with a wireless Connectivity Module that uses ultra-low power (ULP) custom wakeup receivers (WRXs) paired with an ULP node controller (NC) chip. These components can remain always-on at power levels much lower than the inherent standby power of MELs, allowing them to cut off the phantom power to the MELs device while still preserving responsiveness of the MELs devices with low latency when they are needed, either via a wireless wakeup signal received by the WRX or a prediction that the device is needed based on a model.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

Reliability Considerations for Ultra- Low Power Space Applications

NASA, the aerospace community, and other high reliability (hi-rel) users of advanced microelectronic products face many challenges as technology continues to scale into the deep sub- micron region and ULP devices are sought after. Technology trends, ULP microelectronics, scaling and performance tradeoffs, reliability considerations, and spacecraft environments will be presented from a ULP perspective for space applications.

reliability↗