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Conference presentation on hardware acceleration of AI model training, validation, and testing using wafer scale engines, to improve efficiency and effectiveness of carbon management.
The versatility and wide-ranging applicability of the Ising model, originally introduced to study phase transitions in magnetic materials, have made it a cornerstone in statistical physics and a valuable tool for evaluating the performance of emerging computer hardware. Here, we present a novel implementation of the two-dimensional Ising model on Cerebras Wafer-Scale Engine (WSE) – a revolutionary processor that is opening new frontiers in computing. In our deployment of the checkerboard algorithm, we optimized the Ising model to take advantage of the unique WSE architecture. Specifically, we employed a compressed bit representation storing 16 spins on each int16 word, and efficiently distributed the spins over the processing units enabling seamless weak scaling and limiting communications to only immediate neighboring units. Our implementation can handle up to 754 simulations in parallel, achieving an aggregate of over 61.8 trillion flip attempts per second for Ising models with up to 200 million spins. This represents a gain of up to 148 times over previously reported single-devices with a highly optimized implementation on NVIDIA V100 and up to 88 times in productivity compared to NVIDIA H100. Our findings highlight the significant potential of the WSE in scientific computing, particularly in the field of materials modeling.
In this work, compute acceleration of such model training was achieved by taking advantage of extreme workflow parallelism of single-wafer-embedding of the compute resources.
This is a demonstration of WSE/WFA software toward the simulation of CO2 injection into a reservoir.
The evolution of molecular dynamics (MD) simulations has been intimately linked to that of computing hardware. For decades following the creation of MD, simulations have improved with computing power along the three principal dimensions of accuracy, atom count (spatial scale), and duration (temporal scale). Since the mid-2000s, computer platforms have, however, failed to provide strong scaling for MD, as scale-out central processing unit (CPU) and graphics processing unit (GPU) platforms that provide substantial increases to spatial scale do not lead to proportional increases in temporal scale. Important scientific problems therefore remained inaccessible to direct simulation, prompting the development of increasingly sophisticated algorithms that present significant complexity, accuracy, and efficiency challenges. While bespoke MD-only hardware solutions have provided a path to longer timescales for specific physical systems, their impact on the broader community has been mitigated by their limited adaptability to new methods and potentials. In this work, we show that a novel computing architecture, the Cerebras wafer scale engine, completely alters the scaling path by delivering unprecedentedly high simulation rates up to 1.144 M steps/s for 200 000 atoms whose interactions are described by an embedded atom method potential. This enables direct simulations of the evolution of materials using general-purpose programmable hardware over millisecond timescales, dramatically increasing the space of direct MD simulations that can be carried out. In this paper, we provide an overview of advances in MD over the last 60 years and present our recent result in the context of historical MD performance trends.
Creating artificial matter with controllable chirality in a simple and scalable manner brings new opportunities to diverse areas. Here we show two such methods based on controlled vacuum filtration - twist stacking and mechanical rotation - for fabricating wafer-scale chiral architectures of ordered carbon nanotubes (CNTs) with tunable and large circular dichroism (CD). By controlling the stacking angle and handedness in the twist-stacking approach, we maximize the CD response and achieve a high deep-ultraviolet ellipticity of 40 ± 1 mdeg nm -1 . Our theoretical simulations using the transfer matrix method reproduce the experimentally observed CD spectra and further predict that an optimized film of twist-stacked CNTs can exhibit an ellipticity as high as 150 mdeg nm -1 , corresponding to a g factor of 0.22. Furthermore, the mechanical rotation method not only accelerates the fabrication of twisted structures but also produces both chiralities simultaneously in a single sample, in a single run, and in a controllable manner. The created wafer-scale objects represent an alternative type of synthetic chiral matter consisting of ordered quantum wires whose macroscopic properties are governed by nanoscopic electronic signatures and can be used to explore chiral phenomena and develop chiral photonic and optoelectronic devices.
High-k oxides such as SrTiO 3 promise large capacitance, but their dielectric response is often limited by leakage currents due to reduced bandgaps. We show that introducing a thin barrier layer beneath SrTiO 3 is a simple and effective way to suppress leakage and increase charge density. Using hybrid molecular beam epitaxy, we grew uniform SrTiO 3 films on Nb:SrTiO 3 , CaSnO 3 /Nb:SrTiO 3 , and 2-in. SiO 2 /p-Si stacks to directly compare how different barrier layers influence device behavior. Both CaSnO 3 and SiO 2 reduce leakage, but the ultra-wide-bandgap SiO 2 layer enables much higher operating voltages, yielding charge densities exceeding 5 × 10 13 cm −2 at room temperature—more than a fivefold enhancement compared to devices without a barrier layer. This improvement comes with a predictable trade-off: the lower dielectric constant of SiO 2 reduces overall capacitance, making its thickness an important design parameter. Together, these results demonstrate that rational barrier-layer engineering—including wafer-scale integration on Si—provides a clear pathway to achieving higher charge densities in SrTiO 3 -based dielectric devices.
Two-dimensional (2D) crystals have renewed opportunities in design and assembly of artificial lattices without the constraints of epitaxy. However, the lack of thickness control in exfoliated van der Waals (vdW) layers prevents realization of repeat units with high fidelity. Recent availability of uniform, wafer-scale samples permits engineering of both electronic and optical dispersions in stacks of disparate 2D layers with multiple repeating units. In this study, we present optical dispersion engineering in a superlattice structure comprising alternating layers of 2D excitonic chalcogenides and dielectric insulators. By carefully designing the unit cell parameters, we demonstrate greater than 90% narrow band absorption in less than 4 nm of active layer excitonic absorber medium at room temperature, concurrently with enhanced photoluminescence in square-centimetre samples. These superlattices show evidence of strong light–matter coupling and exciton–polariton formation with geometry-tuneable coupling constants. Our results demonstrate proof of concept structures with engineered optical properties and pave the way for a broad class of scalable, designer optical metamaterials from atomically thin layers.
Two-dimensional (2D) semiconductors are highly promising candidates for thin-film transistor applications due to their scalability, transferability, atomic thickness, and relatively high carrier mobility. However, a substantial performance gap remains between individual devices based on single-crystalline 2D films and wafer-scale integrated circuits, primarily due to defects introduced during conventional fabrication processes. Here, we report a diamond-assisted electrode transfer technique for the van der Waals integration of wafer-scale prefabricated electrode arrays onto 2D materials, enabling scalable electronics and optoelectronics. Implemented on metal–organic chemical vapor deposition-grown monolayer molybdenum disulfide, this method forms ultraclean metal–semiconductor interfaces, yielding field-effect transistors with excellent ohmic contacts, a low contact resistance of 400 Ω·μm, and a Schottky barrier height of only 9 meV. Furthermore, we demonstrate a scalable transistor array on monolayer molybdenum disulfide with excellent device performance uniformity, achieving an average field-effect mobility of 30 cm 2 V –1 s –1 and an on/off current ratio exceeding 105. Additionally, high photocurrent and responsivity were demonstrated in the array devices, showing their potential for excellent image detection. We further demonstrate the versatility of this technique by fabricating a Schottky diode array through a single-step transfer of asymmetric electrodes─low work function aluminum and high work function gold─onto monolayer tungsten diselenide. This approach provides a clean, effective solution for contact engineering in 2D materials, offering a viable pathway toward wafer-scale, high-performance 2D electronics, optoelectronics, and integrated circuits.
In this study, epitaxial growth of two-dimensional transition metal dichalcogenides on sapphire has emerged as a promising route to wafer-scale single-crystal films. Steps on the sapphire act as sites for transition metal dichalcogenide nucleation and can impart a preferred domain orientation, resulting in a substantial reduction in mirror twins. Here we demonstrate control of both the nucleation site and unidirectional growth direction of WSe 2 on c-plane sapphire by metal–organic chemical vapour deposition. The unidirectional orientation is found to be intimately tied to growth conditions via changes in the sapphire surface chemistry that control the step edge location of WSe 2 nucleation, imparting either a 0° or 60° orientation relative to the underlying sapphire lattice. The results provide insight into the role of surface chemistry on transition metal dichalcogenide nucleation and domain alignment and demonstrate the ability to engineer domain orientation over wafer-scale substrates.
A major roadblock to scalable quantum computing is phase decoherence and energy relaxation caused by qubits interacting with defect-related two-level systems (TLSs). Native oxides present on the surfaces of superconducting metals used in quantum devices are acknowledged to be a source of TLS that decrease qubit coherence times. Reducing microwave loss by “surface engineering” (i.e., replacing the uncontrolled native oxide of superconducting metals with a thin, stable surface with predictable characteristics) can be a key enabler for pushing performance forward with devices of higher intrinsic quality factor. In this work, we present a novel approach to replace the native oxide of niobium (typically formed in an uncontrolled fashion when its pristine surface is exposed to air) with an engineered oxide, using a room-temperature process that leverages accelerated neutral atom beam (ANAB) technology at 300 mm wafer scale. This ANAB is composed of a mixture of argon and oxygen, with tunable energy per atom, which is rastered across the wafer surface. The ANAB-engineered Nb-oxide thickness was found to vary from 2 to 6 nm depending on ANAB process parameters. The modeling of variable-energy x-ray photoelectron spectroscopy data confirms the thickness and compositional control of Nb surface oxide by the ANAB process. Furthermore, these results correlate well with those from transmission electron microscopy and x-ray reflectometry. Since ANAB is broadly applicable to material surfaces, the present study indicates its promise for modification of the surfaces of superconducting quantum circuits to achieve longer coherence times.
As layered materials, transition metal dichalcogenides (TMDCs) are promising two-dimensional (2D) materials. Interestingly, the characteristics of these materials are transformed from bulk to monolayer. The atomically thin TMDC materials can be a good alternative to group III–V and graphene because of their emerging tunable electrical, optical, and magnetic properties. Although 2D monolayers from natural TMDC materials exhibit the purest form, they have intrinsic defects that limit their application. However, the synthesis of TMDC materials using the existing fabrication tools and techniques is also not immune to defects. Additionally, it is difficult to synthesize wafer-scale TMDC materials for a multitude of factors influencing grain growth mechanisms. While defect engineering techniques may reduce the percentage of defects, the available methods have constraints for healing defects at the desired level. Thus, this holistic review of 2D TMDC materials encapsulates the fundamental structure of TMDC materials, including different types of defects, named zero-dimensional (0D), one-dimensional (1D), and two-dimensional (2D). Moreover, the existing defect engineering methods that relate to both formation of and reduction in defects have been discussed. Finally, an attempt has been made to correlate the impact of defects and the properties of these TMDC materials.
The intent of this presentation is to give a brief look into the future of electronic packaging for microspacecraft applications. Advancements in electronic packaging technology areas have developed to the point where a system engineer's visions, concepts, and requirements for a microspacecraft can now be a reality. These new developments are ideal candidates for microspacecraft applications. These technologies are capable of bringing about major changes in how we design future spacecraft while taking advantage of the benefits due to size, weight, power, performance, reliability , and cost. This presentation will also cover some advantages and limitations of surface mount technology (SMT), multichip modules (MCM), and wafer scale integration (WSI), and what is needed to implement these technologies into microspacecraft.
Van der Waals (vdW) solids can be engineered with atomically precise vertical composition through the assembly of layered two-dimensional materials. However, the artisanal assembly of structures from micromechanically exfoliated flakes is not compatible with scalable and rapid manufacturing. Further engineering of vdW solids requires precisely designed and controlled composition over all three spatial dimensions and interlayer rotation. Here, we report a robotic four-dimensional pixel assembly method for manufacturing vdW solids with unprecedented speed, deliberate design, large area and angle control. We used the robotic assembly of prepatterned 'pixels' made from atomically thin two-dimensional components. Wafer-scale two-dimensional material films were grown, patterned through a clean, contact-free process and assembled using engineered adhesive stamps actuated by a high-vacuum robot. We fabricated vdW solids with up to 80 individual layers, consisting of 100 x 100 μm 2 areas with predesigned patterned shapes, laterally/vertically programmed composition and controlled interlayer angle. This enabled efficient optical spectroscopic assays of the vdW solids, revealing new excitonic and absorbance layer dependencies in MoS 2 . Furthermore, we fabricated twisted $N$-layer assemblies, where we observed atomic reconstruction of twisted four-layer WS 2 at high interlayer twist angles of >= 4°. In conclusion, our method enables the rapid manufacturing of atomically resolved quantum materials, which could help realize the full potential of vdW heterostructures as a platform for novel physics and advanced electronic technologies.
Thin-film epitaxy and epitaxial strain have been widely exploited to tune domain configurations, switching behavior, and ferroic properties in conventional three-dimensional ferroelectric thin films; however, its application to controlling the properties of two-dimensional (2D) ferroelectrics has remained largely unexplored. Here, using SnX (X = Se, S) as a model system, we demonstrate heteroepitaxial control of thickness, strain state, and domain architecture in few-layer ferroelectric SnX via growth on monolayer MoS2 van der Waals (vdW) templates. Compared with conventional growth, MoS2-templated heteroepitaxy promotes epitaxial alignment, yielding ultrathin SnSe films with improved crystalline quality, full areal coverage, and enlarged lateral dimensions. Strong interfacial epitaxial coupling induces pronounced in-plane strain and stabilizes a hierarchical ferroelastic domain architecture, in which long-range 90° stripe domains are further subdivided into nanoscale rotational variants, as revealed by scanning transmission electron microscopy and synchrotron X-ray microscopy. Piezoresponse force microscopy and second-harmonic polarimetry confirm robust in-plane polarization, while ferroelectricity in SnSe is established through polarization-electric field hysteresis and nonvolatile ferroelectric resistive switching with on/off ratios approaching 1000. A nonvolatile, switchable ferroelectric diode effect further evidences direct coupling between polarization and charge transport. Notably, ferroelectric switchability exhibits a strong thickness dependence and is preserved only below ∼10 layers. This vdW heteroepitaxial strategy is further extended to ferroelectric SnS. The seamless heteroepitaxial integration of 2D ferroelectrics with CMOS-compatible, wafer-scale MoS2 templates provides a general and scalable route for strain-enabled structural and ferroelectric engineering in emerging memory and low-power optoelectronic applications.
Surface drying is a critical process in microelectronics wafer fabrication. In order to reduce and eliminate watermarks, many surface drying processes have been studied and used. Most of the wafer foundries currently use drying processes based on Isopropyl Alcohol (IPA), which causes serious safety (fire), health, environmental, and energy efficiency issues. The long-term goal of this project is to develop a fast, effective, chemical-free, and extremely energy efficient wafer drying technology that employs nanosecond laser-induced sub-surface evaporation and explosion. The objectives of this project are to 1) experimentally develop and verify the laser surface drying method, explore and identify how and to what extent various physical parameters influence the drying efficiency and effectiveness; and 2) understand and optimize the underlying thermodynamics in the proposed laser surface drying, including micro/nanoscale sub-surface superheating, evaporation, explosion, and photo/thermochemical bond breaking via atomistic modeling and experimental characterization. Toward these objectives, five tasks have been accomplished successfully, including 1) develop in-lab laser surface drying setup and study the effect of varied laser parameters, 2) use multiscale hybrid-modeling to study and understand the physics of water behavior during drying toward process optimization, 3) investigate the effect of drying conditions on the drying effectiveness, 4) develop a large-scale laser drying scanning system with automatic scanning, and 5) conduct large-scale simulation to study the effect of dopant level and develop strategies for system development toward industry deployment.
Computation in biological neural circuits arises from the interplay of nonlinear temporal responses and spatially distributed dynamic network interactions. Replicating this richness in hardware has remained challenging, as most neuromorphic devices emulate only isolated neuron- or synapse-like functions. Here we introduce an integrated neuromorphic computing platform in which both nonlinear spatiotemporal processing and programmable memory are realized within a single perovskite nickelate material system. By engineering symmetric and asymmetric hydrogenated NdNiO 3 junction devices on the same wafer, we combine ultrafast, proton-mediated transient dynamics with stable multilevel resistance states. Networks of symmetric NdNiO 3 junctions exhibit emergent spatial interactions mediated by proton redistribution, while each node simultaneously provides short-term temporal memory, enabling nanosecond-scale operation with an energy cost of ~0.2 nJ per input. When interfaced with asymmetric output units serving as reconfigurable long-term weights, these networks allow both feature transformation and linear classification in the same material system. Leveraging these emergent interactions, the platform enables real-time pattern recognition and achieves high accuracy in spoken digit classification and early seizure detection, outperforming temporal-only or uncoupled architectures. These results position protonic nickelates as a compact, energy-efficient, CMOS-compatible platform that integrates processing and memory for scalable intelligent hardware.
Very recently, the synthesis of 2D MoS2 and WS2 through pulsed laser-directed thermolysis can achieve wafer-scale and large-area structures, in ambient conditions. In this paper, we report the synthesis of MoS2 and MoS2 oxides from (NH4)2MoS4 film using a visible continuous-wave (CW) laser at 532 nm, instead of the infrared pulsed laser for the laser-directed thermolysis. The (NH4)2MoS4 film is prepared by dissolving its crystal powder in DI water, sonicating the solution, and dip-coating onto a glass slide. We observed a laser intensity threshold for the laser synthesis of MoS2, however, it occurred in a narrow laser intensity range. Above that range, a mixture of MoS2 and MoO2 is formed, which can be used for a memristor device, as demonstrated by other research groups. We did not observe a mixture of MoS2 and MoO3 in the laser thermolysis of (NH4)2MoS4. The laser synthesis of MoS2 in a line pattern is also achieved through laser scanning. Due to of the ease of CW beam steering and the fine control of laser intensities, this study can lead toward the CW laser-directed thermolysis of (NH4)2MoS4 film for the fast, non-vacuum, patternable, and wafer-scale synthesis of 2D MoS2.