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Allerman, Andrew A.

Publications and source records attributed to Allerman, Andrew A..

27 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Origins of epitaxial macro-terraces and macro-steps on GaN substrates

Localized lattice distortions in GaN substrates can serve as nucleation sites for epitaxial macro-steps and macro-terraces. These detrimental macro-scale features give rise to optically hazy homoepitaxial GaN surfaces. After nucleating, these macro-features grow laterally along the surface and coalesce, leading to significant coverage of the wafer surface. Dot-core GaN substrates consisting of a periodic array of cores were used as a defect-engineered system, where dislocations are intentionally concentrated at the cores. The high density of threading dislocations at the cores induced localized lattice distortions. Here, these distortions are associated predominantly with lattice tilt on the order of hundreds of arcsec across ~0.5 mm laterally along the wafer surface. The resulting macro-features that nucleated at these localized distorted sites were made up of macro-terraces with lengths ranging ~30–~150 μm and macro-step heights ranging ~200–~400 nm. Another source of localized distortion was threading screw dislocations or GaN nanopipes that resulted in spiral growth and hillock formation. Based on x-ray topography and optical microscopy measurements, we speculate that the coalescence of hillocks evolves into macro-terraces and macro-steps. While previous studies focused on the substrate miscut as a means to control macro-feature formation, we show that localized lattice tilt from defects is another important contributor to macro-feature formation.

36 MATERIALS SCIENCE↗
DOE OSTI2023

AlGaN High Electron Mobility Transistor for High-Temperature Logic

Here we report on AlGaN high electron mobility transistor (HEMT)-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature-dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data (from 30°C to 500°C) revealed the reference GaN-channel HEMT experienced a 6.9x reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200-nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.

42 ENGINEERING↗
DOE OSTI2022

Demonstration of >6.0-kV Breakdown Voltage in Large Area Vertical GaN p-n Diodes With Step-Etched Junction Termination Extensions

Vertical gallium nitride (GaN) p-n diodes have garnered significant interest for use in power electronics where high-voltage blocking and high-power efficiency are of concern. In this article, we detail the growth and fabrication methods used to develop a large area (1 mm 2 ) vertical GaN p-n diode capable of a 6.0-kV breakdown. We also demonstrate a large area diode with a forward pulsed current of 3.5 A, an 8.3-mΩ$\cdot$cm 2 differential specific ON-resistance, and a 5.3-kV reverse breakdown. In addition, we report on a smaller area diode (0.063 mm 2 ) that is capable of 6.4-kV breakdown with a differential specific ON-resistance of 10.2 mΩ$\cdot$cm 2 , when accounting for current spreading through the drift region at a 45° angle. Finally, the demonstration of avalanche breakdown is shown for a 0.063-mm 2 diode with a room temperature breakdown of 5.6 kV. In this work, these results were achieved via epitaxial growth of a 50-μm drift region with a very low carrier concentration of <1×10 15 cm –3 and a carefully designed four-zone junction termination extension.

42 ENGINEERING↗
DOE OSTI2021

Removing or preventing dry etch-induced damage in Al/In/GaN films by photoelectrochemical etching

A method comprises providing a substrate comprising an n-type Al/In/GaN semiconductor material. A surface of the substrate is dry-etched to form a trench therein and cause dry-etch damage to remain on the surface. The surface of the substrate is immersed in an electrolyte solution and illuminated with above bandgap light having a wavelength that generates electron-hole pairs in the n-type Al/In/GaN semiconductor material, thereby photoelectrochemically etching the surface to remove at least a portion of the dry-etch damage.

Monavarian, Morteza↗