Engineering topics

Arozullah, M.

Publications and source records attributed to Arozullah, M..

7 records

NASA NTRS1980

A microprocessor based high speed packet switch for satellite communications

The architectures of a single processor, a three processor, and a multiple processor system are described. The hardware circuits, and software routines required for implementing the three and multiple processor designs are presented. A bit-slice microprocessor was designed and microprogrammed. Maximum throughput was calculated for all three designs. Queue theoretic models for these three designs were developed and utilized to obtain analytical expressions for the average waiting times, overall average response times and average queue sizes. From these expressions, graphs were obtained showing the effect on the system performance of a number of design parameters.

Arozullah, M.↗

NASA NTRS1980

A microprocessor based high speed packet switch for satellite communications, executive summary

The feasibility of using microprocessors to control satellite-borne packet switching was investigated by designing a packet switch architecture suitable for microprocessor control, using 2900 series components to design the processor(s), and evaluating the packet switch in terms of system throughput, delay, and queue sizes without the packet switch. System architecture for one, three, and multiple processors was designed and evaluated. The production cost of the single processor packet switch is estimated at $500,000, excluding cost of development. The three processor version which can support a maximum throughput of 500,000 packets/sec is estimated to have a production cost of under $100,000. For the multiple processor system, cost is believed to be proportional to throughput, with $1,000,000 for 500,000 packets/sec being the proportionality factor.

Arozullah, M.↗

NASA NTRS1980

Microprocessor utilization in satellite-borne packet switching

The application of a bit slice microprocessor to a satellite-borne packet switch, serving geographically distributed users, is discussed. A system architecture that employs this packet switch is examined, and the performance of the switch is evaluated by obtaining an upper bound on the system throughput.

Burnell, J. F.↗

NASA NTRS1980

A microprocessor based high speed space-borne packet switch

The design and performance evaluation of a single microprocessor based packet switch for use on-board a satellite are presented. The primary design criterion is to maximize the system throughput. A number of protocols and their impact on the switch design are discussed. Stem and processor hardware architectures are described. The flow charts of the software required to accomplish the essential functions are presented and modification needed for use in a multisatellite network are also indicated. Maximum throughput attainable is calculated, desirable characteristics of microprocessors for this application are pointed out. A queue theoretic model of the packet switch has been developed. Analytical relationships of the average waiting times and the queue sizes at the queues and the overall average response time with the various design parameters of the switch have been obtained. A number of graphs showing the effect of variation in the number of input and output lines, data rates, destination functions, speed of output lines and some other design parameters on the performance of the switch are presented and discussed.

Arozullah, M.↗

NASA NTRS1979

A microprocessor based satellite borne packet switch

Design considerations applicable to a space-borne single microprocessor based packet switch are identified. These include system architecture decisions and microprocessor selection. The division of tasks among different subroutines is discussed. The primary design criterion is to maximize throughput. The extension to a multi-satellite network is discussed. The maximum throughput attainable is derived. A queue theoretic model has been developed and expressions for average response times and average queue sizes are obtained. A number of graphs showing the effect of various design parameters on the average response time and the average queue sizes are presented.

Crist, S. C.↗

NASA NTRS1978

A microprocessor based communications multiplexer/concentrator

In the past communications concentrators have been designed using mini-computers. In this work a design for a high speed concentrator (in the megabits range) is developed using the 3000 series bit slice microprocessor. The proposed concentrator realizes the functions of multiplexing of the data arriving on the low speed lines, demultiplexing of the data arriving on the high speed line, including canned responses and code conversion. The basic system hardware configuration and the principles of operation of the multiplexing and the demultiplexing subsystems are presented. The software for these two functions are also presented. Using queueing theory, an estimate of the required buffer size is provided. Possible areas of further improvement are also indicated.

Brown, D. W.↗

NASA NTRS1978

Design of a microprocessor based packet switch

The design of a packet switch incorporating a minicomputer to control and process data packets in a communications system has been reported. This paper proposes a design which uses a 6500 series microprocessor to realize the functions of a message switch in order to evaluate the viability of microprocessors in this application. The proposed design realizes the functions of header analysis, packet security, error control and line prioritization. The system hardware and software are presented together with a brief description of operation.

Carville, D. E.↗