A microprocessor based satellite borne packet switch

Abstract

Design considerations applicable to a space-borne single microprocessor based packet switch are identified. These include system architecture decisions and microprocessor selection. The division of tasks among different subroutines is discussed. The primary design criterion is to maximize throughput. The extension to a multi-satellite network is discussed. The maximum throughput attainable is derived. A queue theoretic model has been developed and expressions for average response times and average queue sizes are obtained. A number of graphs showing the effect of various design parameters on the average response time and the average queue sizes are presented.