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Barry, M.

Publications and source records attributed to Barry, M..

Technology, design, simulation, and evaluation for SEP-hardened circuits

This paper describes the technology, design, simulation, and evaluation for improvement of the Single Event Phenomena (SEP) hardness of gate-array and SRAM cells. Through the use of design and processing techniques, it is possible to achieve an SEP error rate less than 1.0 x 10(exp -10) errors/bit-day for a 9O percent worst-case geosynchronous orbit environment.

Adams, J. R.