NASA NTRS · 19940013879
Technology, design, simulation, and evaluation for SEP-hardened circuits
Abstract
This paper describes the technology, design, simulation, and evaluation for improvement of the Single Event Phenomena (SEP) hardness of gate-array and SRAM cells. Through the use of design and processing techniques, it is possible to achieve an SEP error rate less than 1.0 x 10(exp -10) errors/bit-day for a 9O percent worst-case geosynchronous orbit environment.
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Adams, J. R., Allred, D., Barry, M., Rudeck, P., Woodruff, R., Hoekstra, J., Gardner, H.. 1991-01-01. Technology, design, simulation, and evaluation for SEP-hardened circuits. https://ntrs.nasa.gov/citations/19940013879
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