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Beausoleil, Raymond G.

Publications and source records attributed to Beausoleil, Raymond G..

How to Build a Quantum Supercomputer: Scaling from Hundreds to Millions of Qubits

In the span of four decades, quantum computation has evolved from an intellectual curiosity to a potentially realizable technology. Today, small-scale demonstrations have become possible for quantum algorithmic primitives on hundreds of physical qubits and proof-of-principle error-correction on a single logical qubit. Nevertheless, despite significant progress and excitement, the path toward a full-stack scalable technology is largely unknown. There are significant outstanding quantum hardware, fabrication, software architecture, and algorithmic challenges that are either unresolved or overlooked. These issues could seriously undermine the arrival of utility-scale quantum computers for the foreseeable future. Here, we provide a comprehensive review of these scaling challenges. We show how the road to scaling could be paved by adopting existing semiconductor technology to build much higher-quality qubits, employing system engineering approaches, and performing distributed quantum computation within heterogeneous high-performance computing infrastructures. These opportunities for research and development could unlock certain promising applications, in particular, efficient quantum simulation/learning of quantum data generated by natural or engineered quantum systems. To estimate the true cost of such promises, we provide a detailed resource and sensitivity analysis for classically hard quantum chemistry calculations on surface-code error-corrected quantum computers given current, target, and desired hardware specifications based on superconducting qubits, accounting for a realistic distribution of errors. Furthermore, we argue that, to tackle industry-scale classical optimization and machine learning problems in a cost-effective manner, heterogeneous quantum-probabilistic computing with custom-designed accelerators should be considered as a complementary path toward scalability.

Mohseni, Masoud↗

Energy efficient photonic memory based on electrically programmable embedded III-V/Si memristors: switches and filters

Abstract Over the past few years, extensive work on optical neural networks has been investigated in hopes of achieving orders of magnitude improvement in energy efficiency and compute density via all-optical matrix-vector multiplication. However, these solutions are limited by a lack of high-speed power power-efficient phase tuners, on-chip non-volatile memory, and a proper material platform that can heterogeneously integrate all the necessary components needed onto a single chip. We address these issues by demonstrating embedded multi-layer HfO 2 /Al 2 O 3 memristors with III-V/Si photonics which facilitate non-volatile optical functionality for a variety of devices such as Mach-Zehnder Interferometers, and (de-)interleaver filters. The Mach-Zehnder optical memristor exhibits non-volatile optical phase shifts > π with ~33 dB signal extinction while consuming 0 electrical power consumption. We demonstrate 6 non-volatile states each capable of 4 Gbps modulation. (De-) interleaver filters were demonstrated to exhibit memristive non-volatile passband transformation with full set/reset states. Time duration tests were performed on all devices and indicated non-volatility up to 24 hours and beyond. We demonstrate non-volatile III-V/Si optical memristors with large electric-field driven phase shifts and reconfigurable filters with true 0 static power consumption. As a result, co-integrated photonic memristors offer a pathway for in-memory optical computing and large-scale non-volatile photonic circuits.

Cheung, Stanley (ORCID:0000000248860013)↗

Ultra-power-efficient heterogeneous III–V/Si MOSCAP (de-)interleavers for DWDM optical links

We discuss the design and demonstration of various III–V/Si asymmetric Mach–Zehnder interferometer (AMZI) and ring-assisted AMZI (de-)interleavers operating at O-band wavelengths with 65 GHz channel spacing. The wafer-bonded III–V/Si metal-oxide-semiconductor capacitor (MOSCAP) structure facilitates ultra-low-power phase tuning on a heterogeneous platform that allows for complete monolithic transceiver photonic integration. The second- and third-order MOSCAP AMZI (de-)interleavers exhibit cross-talk (XT) levels down to − 22 dB and − 32 dB with tuning powers of 83.0 nW and 53.0 nW, respectively. The one-, two-, and three-ring-assisted MOSCAP AMZI (de-)interleavers have XT levels down to − 27 dB, − 22 dB, and − 20 dB for tuning powers of 10.0 nW, 7220.0 nW, and 33.6 nW, respectively. The leakage current density is measured to be in the range of 1.6 – 27 μA / cm 2 . To the best of our knowledge, we have demonstrated for the first time, athermal III–V/Si MOSCAP (de-)interleavers with the lowest XT and reconfiguration power consumption on a silicon platform.

Cheung, Stanley (ORCID:0000000248860013)↗

32 Gbps heterogeneously integrated quantum dot waveguide avalanche photodiodes on silicon

We report a heterogeneous GaAs-based quantum dot (QD) avalanche photodiode (APD) on silicon with an ultralow dark current of 10 pA at − <#comment/> 1 V , 3 dB bandwidth of 20 GHz and record gain-bandwidth product (GBP) of 585 GHz. Furthermore, open eye diagrams up to 32 Gb/s are demonstrated at 1310 nm. The k-factor has been measured for these devices to be as low as 0.14. A polarization dependence on gain and bandwidth has been observed and investigated. This shows the potential to integrate a high-speed receiver in a wavelength division multiplexing (WDM) system on a QD-based silicon photonics platform.

Tossoun, Bassem↗