Engineering topics
Boyer, Jacob T.
Publications and source records attributed to Boyer, Jacob T..
24% Single-Junction GaAs Solar Cell Grown Directly on Growth-Planarized Facets Using Hydride Vapor Phase Epitaxy
A 24%-efficient single-junction GaAs solar cell grown directly on a faceted, spalled (100) GaAs substrate after in situ planarization growth by hydride vapor phase epitaxy (HVPE) is achieved. Controlled spalling, a promising low-cost substrate reuse technique, produces large facets in (100)-oriented GaAs substrates due to the orientation of the fracture planes used for lift-off. Planarization by HVPE offers a path toward direct use of these spalled substrates without costly polishing steps. In this report the growth rate anisotropy enabling planarization arising from diffusion and differences in the adsorption of growth species on {n11}B-type facets relative to (100) is determined. Consecutive planarization and device growth that results in a solar cell with a minimal performance difference relative to a control cell grown on an epitaxy-ready substrate are demonstrated. These results show that controlled spalling coupled with HVPE planarization is a viable pathway for lowering the cost of III-V photovoltaics.
GaAs solar cells grown on acoustically spalled GaAs substrates with 27% efficiency
Acoustic spalling presents a potentially low-cost reuse pathway for III–V epitaxial growth substrates via exfoliation of device layers with recovery and reuse of the substrate. However, surface features formed during spalling can reduce the performance of subsequently grown devices. Here, we develop an understanding of how the surface morphology of acoustically spalled substrates affects GaAs solar cell performance and develop strategies to mitigate these impacts. We demonstrate that minor planarization of the surface by wet chemical etching and/or epitaxial growth, or the redesign of the device structure to thicken critical layers, prevents performance degradation. Using these strategies, we demonstrate a 0.25 cm 2 single-junction GaAs device with 26.9% ± 0.2% photovoltaic conversion efficiency under the AM1.5G spectrum grown on an acoustically spalled substrate. These results enable the growth of high-performance III–V devices on non-traditional substrates with the potential for significantly reduced device costs.
AlInP-passivated III–V solar cells grown by dynamic hydride vapor-phase epitaxy
We report the development of AlInP-passivated solar cells grown by dynamic hydride vapor-phase epitaxy (D-HVPE) with AM1.5G efficiencies of 26.0% for single-junction (1J) GaAs cells and 28.0% for GaInP/GaAs (2J) tandems. We compare the device performance of solar cells passivated with AlInP versus control cells passivated with GaInP, which has already enabled near-unity carrier collection in GaAs solar cells. 1J devices passivated with either AlInP or GaInP have an identical open-circuit voltage (V OC ) of 1.06 V and long-wavelength current collection near 95%, indicating that both window materials provide a similar degree of passivation. Adding AlInP passivation to each solar cell structure improves the current collection by 1.3 and 1 mA/cm 2 for the 1J and 2J, respectively. The AlInP also results in a top cell V OC boost of ~40 mV relative to a tandem device passivated only by a thin, highly doped GaInP emitter. Secondary-ion mass spectrometry measurements indicate that although O and Si both incorporate in the AlInP window, they do not appear in the subsequently grown absorber layers and do not impact its ability to passivate the front surface. We expect that these achievements, along with continued optimization, will enable parity of hydride vapor-phase epitaxy (HVPE)-grown device efficiencies with state-of-the-art devices grown by other epitaxial methods in the near future.
23.4% monolithic epitaxial GaAsP/Si tandem solar cells and quantification of losses from threading dislocations
A 2-terminal, dual-junction, epitaxially integrated, GaAsP/Si tandem solar cell with an 3rd party certified efficiency of 23.4 % was fabricated via MOCVD growth on an ex-situ produced Si sub cell. The drastic efficiency improvement over the authors previous peer-reviewed demonstration of such a device architecture is examined. Critical advancements in top cell design to maximize short wavelength response were critical in enabling improved top cell response. An in-depth analysis of this champion tandem cell has identified key loss mechanisms which elucidate the pathway for further efficiency gains. First, voltage dependent collection efficiency in the GaAsP top cell is the primary cause of fill factor losses currently limiting efficiency. Analysis of spectrally resolved I–V measurements and analytical device modeling and indicate poor diffusion length due to elevated dislocation densities as the likely cause for the voltage dependent collection efficiency. Second, modeling for the GaAs 0.75 P 0.25 top cell, using experimental data at multiple dislocation densities, provides quantitative understanding of the current and voltage losses associated with threading dislocations providing a clear efficiency pathway with reduction in dislocation density. Finally, Si subcell modeling identifies the pathway for further Si subcell advances over the present, simplistic design, which has yet to employ the known benefits of rear surface texture or dielectric passivation.
Metamorphic Tunnel Junctions Grown Via MOCVD Designed for GaAs 0.75 P 0.25 /Si Tandem Solar Cells
A high-performance metamorphic Al 0.2 Ga 0.8 As 0.75 P 0.25 /GaAs 0.75 P 0.25 heterojunction tunnel junction structure was developed for application to monolithic epitaxial GaAs 0.75 P 0.25 /Si 1.7 eV/1.1 eV bandgap tandem solar cells produced via metal-organic chemical vapor deposition. Doping optimization focused on both bulk doping concentrations and mitigating the transient incorporation effects that otherwise causes non-abrupt doping profiles in the Te doped layer. Furthermore, these efforts resulted in a fully-relaxed metamorphic tunnel diode at the target lattice constant having a peak tunneling current density (JP) of 279.1 A·cm –2 and a zero-bias resistance area product (RA) of 3.0×10 –4 Ω·cm 2 . After post-growth annealing to emulate the thermal load of the GaAs 0.75 P 0.25 top cell growth and elimination of the performance enhancing carbon activation anneal, the device achieved JP = 13.1 A·cm –2 and RA = 1.5×10 –3 Ω·cm 2 . These worst-case values are very promising as they enable the operation of GaAs 0.75 P 0.25 /Si tandems under one-sun AM1.5G illumination with negligible series resistance and at AM1.5D concentrations up to 240 suns with only 0.1% absolute efficiency loss.
Improving GaAsP/Si Tandem Solar Cells Using Silicon Passivated Contacts
The degradation of photocarrier bulk lifetime in Si wafer substrates during the heteroepitaxial growth of III-V materials has been widely reported and is known to limit the efficiency of III-V/Si tandem solar cells. There have been prior strategies to protect Si lifetime in III-V growth chambers, but most require the use of a protective layer that must be removed in subsequent device processing. It would be advantageous for protective layers to remain an active part of the device. In this work, we demonstrate that a polycrystalline silicon (poly-Si) passivated contact can protect the minority carrier lifetime of the Si base wafer during the organometallic vapor phase epitaxy of III-V materials on silicon substrates.
Reduced Dislocation Introduction in III–V/Si Heterostructures with Glide-Enhancing Compressively Strained Superlattices
The novel use of a GaAs y P 1-y /GaP compressively-strained superlattice (CSS) to provide enhanced control over misfit dislocation (MD) evolution and threading dislocation density (TDD) during GaP/Si metamorphic heteroepitaxy is demonstrated. Here, the insertion of the CSS just after critical thickness, and thus prior to substantial dislocation introduction, is found to yield significantly reduced TDD in relaxed, 500 nm thick, n-type GaP/Si versus comparable control samples. The impact of CSS period count on average TDD and the overall dislocation network morphology was examined, supported by quantitative microstructural characterization, revealing a nearly 20× relative TDD reduction (to 2.4 ± 0.4×10 6 cm -2 ) with a 3-period CSS structure. A similarly low TDD (3.0 ± 0.6×10 6 cm -2 ) is maintained when the resultant n-GaP/Si virtual substrate is used for the growth of a subsequent n-type GaAs 0.75 P 0.25 -terminal GaAs y P 1-y step-graded metamorphic buffer. Although the physical mechanism for TDD reduction provided by these structures is not yet entirely understood, this initial work suggests that enhanced glide dynamics of MDs at or within the CSS placed early in the growth leads to a reduction in the total number of dislocations introduced overall, as opposed to annihilation-based reduction that occurs in conventional strained-layer superlattice dislocation filter approaches.
The Critical Role of AlInP Window Design in III–V Rear-Emitter Solar Cells
This article highlights the critical role of window design on short circuit carrier collection in rear-emitter solar cells, as demonstrated through modeling and experiment using metamorphic GaAs y P 1-y . Ultimately, if the window design is not carefully considered, surface depletion caused by Fermi level pinning at the window/air interface can extend into regions of active collection resulting in a large increase in effective window/base interface recombination velocity. This was experimentally shown here to result in a potential AM1.5G photocurrent loss of 8.1 mA/cm 2 , or nearly 50%, based on integrated internal quantum efficiency (IQE). Associated IQE modeling and curve fitting indicate that the effective IRV at the GaAs 0.75 P 0.25 /Al 0.64 In 0.36 P interface is increased by multiple orders of magnitude when the window is not sufficiently thick or doped to fully contain the surface depletion to within the window layer. Calculations of the surface depletion depth as a function of doping and the surface Fermi pinning energy level provides insight into the fundamental limits of window thickness. As a result, this allows the estimation of the Al 0.64 In 0.36 P surface pinning level to be at least 1.25 eV below the conduction band edge, or in the bottom half of the bandgap.