Engineering topics
Publications and source records attributed to Constable, R. C..
Faults in plated wire memories are identified and located from outside of system by applying electrical impulses and analyzing their reflectance in technique of Time-Domain Reflectometry (TDR). Intermittent faults are easier to find because memory system is not disturbed by probing or disassembly.
Technique measures performance of plated-wire memories. Strobe-margin test (SMT) utilizes worst-case testing and automatically gives exact strobe margin. Test is automatic; thus, memory system-level test is superior to tests at component level that use artificial test conditions. Test is significant tool in design and test of plated-wire memory systems. It can rapidly quantify memory-system margin on each production unit and impact of any design changes.